MIM Capacitor Contact Via Etching for Conformal Barrier Layers
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Solution Overview
Problem
Conventional etching processes for forming contact vias in Metal-Insulator-Metal (MIM) capacitors in semiconductor devices result in non-uniform barrier and seed layers, leading to reliability issues and voltage breakdown due to the redeposition of metal fluoride byproducts, which cause uneven etching rates and defects.
Innovation Solution
A method involving multiple etch processes using different etchants, including fluorine-containing and chlorine-containing etchants, with controlled power applications and wet cleaning steps to achieve substantially linear sidewalls and prevent redeposition, ensuring conformal deposition of barrier and seed layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional single etching process is used to form contact vias through MIM capacitors, then the manufacturing process is simple and fast, but the etching rate becomes non-uniform due to redeposition of metal fluoride byproducts, resulting in non-conformal barrier and seed layers
Solution Approach 1:
The patent divides the single etching process into multiple sequential etching steps (first etching process, second etching process, third etching process) with different etchants and parameters. Each step targets specific layers with optimized conditions, preventing metal fluoride redeposition issues and ensuring uniform barrier and seed layer formation throughout the contact via structure.
Solution Approach 2:
The patent changes multiple parameters across different etching steps including etchant composition (fluorine-containing vs. chlorine-containing), power settings (bias power and source power levels), and pressure conditions. These parameter variations optimize the etching rate and selectivity for each layer, achieving conformal layer deposition while managing the complexity of the multi-step process.
2Productivity
If fluorine-containing etchants are used for etching MIM capacitor layers, then the etching rate is high, but metal fluoride byproducts are redeposited on sidewalls causing non-conformal barrier layers
Solution Approach 1:
The patent segments the etching process to use fluorine-containing etchants only in the first etching step where high etching rate is needed to penetrate throughlier layers. Subsequent steps use chlorine-containing etchants that etch at lower rates but do not produce redeposited metal fluoride byproducts, thus achieving both high overall productivity and conformal barrier layer formation.
Solution Approach 2:
The patent introduces an intermediate etching step using chlorine-containing etchant between the initial fluorine-based etching and final etching steps. This intermediate step acts as a mediator that removes previously deposited metal fluoride byproducts and prepares the surface for conformal barrier layer deposition, bridging the gap between high-rate etching and precise conformal deposition.
3Adaptability or versatility
If the contact via opening has a stepped structure, then it can accommodate the MIM capacitor structure, but the barrier and seed layers deposited on sidewalls are non-conformal leading to reliability issues
Solution Approach 1:
The patent applies controlled parameter changes in the etching process, specifically adjusting bias power and source power settings in different etching steps, to achieve a substantially linear sidewall profile in the contact via opening. This linear profile, while maintaining adaptability to the MIM capacitor structure, ensures uniform barrier and seed layer deposition that prevents voltage breakdown and improves reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures reliable and uniform formation of contact vias with conformal barrier and seed layers, preventing voltage breakdown and improving the overall reliability of the semiconductor device fabrication process.
Implementation Method 1
performing a first etch process to form an opening that extends through the fourth dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the third dielectric layer, performing a third etch process to further extend the opening into the third dielectric layer
Implementation Method 2
wet cleaning steps to achieve substantially linear sidewalls and prevent redeposition
Data Source
AI summary
A method includes providing a workpiece. The workpiece includes a substrate, a first dielectric layer over the substrate, a lower contact feature vertically extending through the first dielectric layer, a second dielectric layer over the lower contact feature and the first dielectric layer, a third dielectric layer over the second dielectric layer, a metal-insulator-metal (MIM) structure over the third dielectric layer, and a fourth dielectric layer over the MIM structure. The method further includes performing a first etch process to form an opening through the fourth dielectric layer to expose the MIM structure; performing a second etch process to extend the opening through the MIM structure to expose the third dielectric layer; performing a third etch process to further extend the opening into the third dielectric layer; and performing a fourth etch process to further extend the opening through the second dielectric layer to expose the lower contact feature.