MIM Decoupling Capacitors Under Contact Pads

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The integration of metal-insulator-metal (MIM) decoupling capacitors on-chip is limited by the available area and routing lines, leading to increased chip size due to the significant space requirements and complex placement needs.

Innovation Solution

Placing one or more MIM decoupling capacitors directly under external contact pads, with the option to include dummy MIM capacitors, allows for a more efficient use of chip area and reduces overall chip size by utilizing the space under the contact pads for capacitor arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If MIM decoupling capacitors are placed on-chip to increase capacitance, then the decoupling capability is improved, but the chip area increases significantly

Engineering Contradiction:
Improvedecoupling capabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent utilizes the vertical dimension by placing MIM capacitors directly under the contact pad, effectively using the area under the pad that would otherwise be unused. This three-dimensional placement strategy allows the capacitor to occupy space in the vertical direction rather than only in the planar area, thereby improving decoupling capability without significantly increasing the overall chip area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The MIM capacitor is nested under the contact pad structure, with the capacitor occupying the space beneath the pad. This nesting approach allows the capacitor to be integrated into the existing contact pad area, utilizing the vertical space under the pad to house the capacitor structure without requiring additional lateral space.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If MIM capacitors are used to increase capacitance density, then the capacitance per unit area is improved, but the routing complexity and placement difficulty increase

Engineering Contradiction:
Improvecapacitance densityVSAvoidrouting complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The contact pad area serves multiple functions: it provides the external electrical connection interface and simultaneously houses the MIM decoupling capacitor beneath it. This multi-functionality eliminates the need for separate routing to connect the capacitor, as the pad itself provides the electrical connection, thereby reducing routing complexity while maintaining high capacitance density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The contact pad structure serves its own electrical connection function while also providing the housing and electrical connection for the underlying capacitor. The capacitor utilizes the pad's electrical infrastructure, eliminating the need for additional complex routing to connect the capacitor to the power lines, thus simplifying the overall routing architecture.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables a higher capacitance density, such as 5 fF/cell or 85 fF/μm² in a 40 nm design, while maintaining standard semiconductor processing compatibility, thus addressing the area constraints and improving chip design efficiency.

Implementation Method 1

MIM capacitors comprise metallic layers with a dielectric layer interposed therebetween

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

MIM capacitors comprise metallic layers with a dielectric layer interposed therebetween formed in a trench of a dielectric layer

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS8866260B2MIM decoupling capacitors under a contact pad
Publication Date: 2014.10.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8866260B2 patent drawing
  • US8866260B2 patent drawing
  • US8866260B2 patent drawing

AI summary

An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of Vdd and Vss, and the top plate of the decoupling capacitors is electrically coupled to the other. The decoupling capacitors may include an array of decoupling capacitors formed under the external contact pads and may include one or more dummy decoupling capacitors. The one or more dummy decoupling capacitors are MIM capacitors in which at least one of the top plate and the bottom plate is not electrically coupled to an external contact pad.