3D MIM eFuse Memory Cell Layout for Higher Chip Density
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Solution Overview
Problem
The challenge is to reduce the area occupied by eFuse memory cells in integrated circuits (ICs) as the size reduction of eFuse memory devices has not kept pace with the advancement of IC features, leading to a desire for a more compact eFuse memory cell structure.
Innovation Solution
The eFuse memory cell structure is redesigned with access transistors formed over the eFuse resistor in a metallization layer, connected through one or more metallization layers and via structures, and peripheral circuits like power switches and header circuits are positioned above the eFuse resistors and control circuits, allowing for a reduced cell area and increased memory chip density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If eFuse memory cells are formed with traditional lateral configuration, then the device structure is simple and easy to manufacture, but the cell area is large and does not scale with IC feature size reduction
Solution Approach 1:
The patent transitions from a traditional lateral (2D planar) configuration to a vertical (3D stacked) configuration. The access transistor is positioned above the eFuse resistor in the vertical direction, with connections established through metallization layers and vias. This dimensional change enables significantly reduced cell area while maintaining the 1T1R functional structure, directly resolving the contradiction between area reduction and structural simplicity.
2Quantity of substance
If access transistors and peripheral circuits are laterally arranged, then the layout is simple, but the memory chip density is low
Solution Approach 1:
The patent implements a nested arrangement where the access transistor is positioned above the eFuse resistor, with peripheral circuits (power switches and header circuits) stacked above the eFuse resistors and control circuits. This vertical nesting enables multiple functional blocks to occupy the same lateral footprint, significantly increasing memory chip density while managing interconnect complexity through systematic metallization layer design.
Data Source
AI summary
A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.