MIM ESD Protection Circuit in Liquid Crystal Display
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Solution Overview
Problem
Conventional liquid crystal display devices with ESD protection circuits using TFTs require significant space, have complex structures, and exhibit suboptimal diode characteristics due to the need for multiple TFTs per bus line and quadratic current-voltage relationships.
Innovation Solution
Implementing an MIM (Metal-Insulator-Metal) structure as the ESD protection circuit, with a thin film portion in the gate insulating film and a gate bus layer, allowing for a more compact and integrated design by connecting multiple MIMs in series, and using a varied exposure mask process to simplify manufacturing without increasing photolithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a TFT saturation region operation is used for the ESD protection circuit, then the device can be protected from electrostatic discharge, but the circuit requires a relatively wide space and has a complicated structure
Solution Approach 1:
The patent extracts the essential function of the ESD protection circuit (diode characteristic) and implements it using a simplified structure with source and drain electrodes directly forming the protection function, removing the need for complex TFT saturation region operation and light shield films, thereby reducing the occupied area while maintaining ESD protection capability
Solution Approach 2:
Instead of using TFTs to create diode characteristics through saturation region operation, the patent inverts the approach by directly forming a diode structure using source and drain electrodes with appropriate doping, eliminating the need for TFT complexity and reducing the circuit footprint
2Reliability
If a TFT saturation region operation is used for the ESD protection circuit, then the device can be protected from electrostatic discharge, but the current rises with respect to the voltage like a quadratic curve which is not preferable from the standpoint of diode characteristic
Solution Approach 1:
The patent extracts only the necessary diode characteristic function from the TFT structure, using directly doped source and drain regions to form the diode, thereby achieving excellent diode characteristics with linear current-voltage relationship in the forward bias region, suitable for ESD protection applications
Solution Approach 2:
The patent changes the operational parameters by using direct diode structure instead of TFT saturation region, altering the current-voltage relationship from quadratic to exponential characteristic, which provides better diode behavior for ESD protection with lower forward voltage drop and more controlled current flow
3Reliability
If multiple TFTs per bus line are required for the ESD protection circuit, then the device can be protected from electrostatic discharge, but the device complexity increases
Solution Approach 1:
The patent extracts the ESD protection function from the TFT-based implementation and realizes it using a simple diode structure formed by doped source and drain electrodes, eliminating the need for multiple TFTs and associated gate structures, thereby reducing device complexity while maintaining protection capability
Solution Approach 2:
The patent merges the ESD protection function with the existing source and drain electrode structures, integrating the diode characteristic directly into the transistor electrodes without requiring separate TFT components, thereby reducing the number of devices per bus line and simplifying the overall circuit architecture
Data Source
AI summary
A source electrode and a drain electrode on a silicon oxide film (31) each has a double-layered structure of an ITO film (32), a transparent electrode, and a metal film (33) formed on the ITO film (32). A gap (35), no source electrode and drain electrode region, is formed between the source electrode and the drain electrode. A silicon nitride film (34) (a gate insulating film) is formed on the source electrode and the drain electrode and in the gap (35). The silicon nitride film (34) is a first region D1 having a relatively large thickness and a second region D2 having a relatively small thickness. The region D2 of the silicon nitride film (34) is provided with an MIM structure. A gate bus layer (36) is formed on the silicon nitride film (34). An MIM structure is formed in the second region D2.