MIM Capacitor and RDL Layout for Flat, Reliable Semiconductor Interconnects
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the complexity of processing and manufacturing integrated circuits due to the scaling-down process, which increases the difficulty of forming robust metal-insulator-metal (MIM) capacitors and interconnect structures.
Innovation Solution
A method is introduced to form via structures and redistribution layers (RDL) separately, followed by planarization processes, allowing for thicker passivation layers and reducing defects, thereby enhancing the robustness of MIM structures and improving the reliability of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the scaling-down process is used to increase functional density, then production efficiency is improved and costs are lowered, but the complexity of processing and manufacturing increases and reliability decreases
Solution Approach 1:
The patent divides the formation process into separate sequential steps: first forming via structures through the MIM capacitor, then forming the redistribution layer separately. This segmentation allows each structure to be optimized independently, improving reliability while maintaining the scaled-down geometry required for high functional density
Solution Approach 2:
The via structures are formed in advance before the redistribution layer is deposited. This preliminary action allows for proper planarization and stress management before adding the metal layer, ensuring reliable interconnect structures at scaled dimensions
2Ease of manufacture
If conventional simultaneous formation of via structures and redistribution layers is used, then processing steps are reduced, but defects increase and robustness decreases
Solution Approach 1:
The patent separates the formation of via structures and redistribution layers into distinct process steps. This allows each structure to be formed with optimal parameters and proper planarization, achieving high manufacturing precision and robustness while maintaining reasonable process complexity
Solution Approach 2:
A planarization layer is introduced as an intermediary between the via structure formation and the redistribution layer deposition. This intermediary layer enables proper surface preparation and stress management, ensuring robust interconnect structures
Data Source
AI summary
A semiconductor structure includes a metal-insulator-metal (MIM) structure sandwiched between first passivation layers over a substrate. The semiconductor structure also includes via structures through the MIM structure and the first passivation layers. The semiconductor structure further includes redistribution layer (RDL) structures over the via structures. In addition, the semiconductor structure includes a second passivation layer between and over the RDL structures. A bottom surface of the second passivation layer is lower than a topmost surface of the passivation layers.