MIM Capacitor Topography Planarization for Flat Seed Layer Formation
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Solution Overview
Problem
The uneven topology of MIM capacitors during fabrication leads to errors in forming conductive structures due to angled seed layer surfaces causing improper development of photoresist, resulting in lower reliability and yield.
Innovation Solution
Forming a conductive structure with a metal core disposed over a base conductive layer having a substantially flat upper surface, achieved through planarization processes and additional electrochemical plating, to mitigate errors in lithographic radiation reflections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MIM capacitors are formed with standard fabrication processes, then the capacitor structure is created, but the uneven topology causes angled seed layer surfaces leading to lithographic errors
Solution Approach 1:
A planarization layer is formed over the MIM capacitor structure before subsequent lithographic steps. This preliminary planarization action creates a flat surface for the seed layer, preventing the angled surface problems that would otherwise occur during later processing steps.
Solution Approach 2:
The planarization layer acts as an intermediary element between the uneven MIM capacitor structure and the seed layer. This intermediate layer absorbs the topography variations, providing a uniform surface that eliminates lithographic errors while allowing both the capacitor structure and seed layer to maintain their required characteristics.
2Manufacturing precision
If additional planarization processes are performed to flatten the surface, then lithographic accuracy improves, but fabrication complexity and process time increase
Solution Approach 1:
The planarization layer is formed using deposition parameters and material selection that enable surface flattening through controlled physical or chemical processes. By adjusting deposition conditions, thickness, and material properties, the layer achieves the required flatness while minimizing the number of additional process steps needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The flat upper surface of the base conductive layer reduces erroneous reflections, improving the process window for lithography and reducing errors in conductive structure formation, enhancing reliability and yield.
Implementation Method 1
achieved through planarization processes
Implementation Method 2
additional electrochemical plating
Implementation Method 3
reduces erroneous reflections, improving the process window for lithography
Data Source
AI summary
Some embodiments relate to an integrated chip including a first metal insulator metal (MIM) capacitor disposed over a substrate. The integrated chip further includes a second MIM capacitor disposed over the substrate. The first MIM capacitor has a first outer sidewall facing a second outer sidewall of the second MIM capacitor. A dielectric structure is arranged over and laterally between the first MIM capacitor and the second MIM capacitor. A base conductive layer is arranged between the first MIM capacitor and the second MIM capacitor and has a substantially flat upper surface. A metal core arranged on the substantially flat upper surface of the base conductive layer.