MIM Transistor Nanoroughness Gate Control
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Solution Overview
Problem
MOS transistors face challenges in miniaturization due to short channel effects, difficulty in achieving thin gate oxides, high costs of SOI structures, and poor isolation between CMOS transistors, leading to inefficiencies in controlling channel inversion and increasing the integrated surface area.
Innovation Solution
A Metal-Insulator-Metal (MIM) transistor structure is introduced, featuring a very thin conducting layer (1-5 atoms thick) with an insulated gate and electrodes on both sides, formed on an insulating layer over a semiconductor substrate, where the substrate is connected to a determined voltage and the surface beneath the transistor has nanoroughness, allowing for complementary transistors with opposite conductivity types to be adjacent without insulating regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If MOS transistor dimensions are reduced to achieve miniaturization, then device size is reduced, but short channel effects occur resulting in partial control of channel inversion
Solution Approach 1:
The patent changes the fundamental parameters of the transistor structure by replacing the traditional MOS configuration with a MIM structure featuring a conducting layer only 1-5 atoms thick. This extreme thinning of the conducting layer parameter enables total gate control while maintaining miniaturization, as the gate field can now effectively penetrate through the entire conducting layer thickness without suffering from short channel effects.
Solution Approach 2:
The patent transitions from a planar MOS structure to a vertically stacked MIM structure with the gate positioned beneath the conducting layer. This dimensional reconfiguration allows the gate field to exert complete control over the conducting channel from below, eliminating the partial control issue that plagues scaled-down MOS transistors.
2Reliability
If gate oxide is made thinner to improve control, then gate control is improved, but it becomes difficult to obtain sufficiently thin gate oxide
Solution Approach 1:
The patent inverts the traditional MOS structure by placing the gate beneath the conducting layer instead of above it. This inversion eliminates the need for ultra-thin gate oxides, as the gate now directly controls the conducting layer from below through the insulating layer, achieving total control without the manufacturing difficulties of thinning the oxide further.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the gate and the conducting layer. This intermediary enables effective gate control while avoiding the need for extremely thin gate oxides, as the insulating layer provides the necessary electrical isolation while allowing the gate field to penetrate and control the conducting channel.
3Reliability
If SOI structures are used to achieve thin semiconducting layers, then transistor performance is improved, but cost becomes very high
Solution Approach 1:
The patent replaces the expensive SOI (Silicon-On-Insulator) structure with a MIM structure using a conducting layer only 1-5 atoms thick. This alternative approach achieves superior transistor performance without requiring costly SOI fabrication processes, thereby significantly reducing manufacturing costs while maintaining or improving device performance.
4Reliability
If shallow isolation trenches or insulating SOI wells are used for CMOS isolation, then transistor isolation is achieved, but large area of lost space results
Solution Approach 1:
The patent merges the transistor structure with the isolation function by designing the MIM transistor with electrodes extending to the substrate edges. This integration eliminates the need for separate isolation structures like shallow trench isolation or insulating wells, as the transistor structure itself provides the necessary electrical isolation, thereby maximizing the usable chip area.
Solution Approach 2:
The MIM transistor structure serves multiple functions simultaneously: it provides the transistor switching function while also providing electrical isolation to the substrate. This multi-functionality eliminates the need for dedicated isolation structures, reducing the overall chip area required while maintaining effective transistor isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution eliminates the short channel effect, provides total gate control over the channel, reduces integrated surface area, simplifies technology, enhances switch speed, and maintains low resistance in the conducting state, while differentiating ON and OFF states effectively.
Implementation Method 1
the surface in contact with the underside of the transistor is treated to have a nanoroughness
Data Source
AI summary
The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.