3D MIM Trench Capacitor Layout for High Capacitance in Tight Footprints
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Solution Overview
Problem
The challenge of integrating metal-insulator-metal (MIM) capacitors in densely packed integrated circuits with limited available footprint, as traditional planar capacitors struggle to scale effectively with increasing device density.
Innovation Solution
Formation of MIM trench capacitors within the interconnect region above semiconductor devices, utilizing a serpentine design that increases surface area without significantly increasing plan footprint, by running electrodes along the sidewalls and top surfaces of dielectric fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional planar MIM capacitors are used, then the capacitor structure is simple to manufacture, but the capacitance per unit area is insufficient and footprint is large
Solution Approach 1:
The patent transitions from planar 2D capacitor structures to 3D vertical trench structures. The MIM capacitor is formed in a trench extending vertically through the substrate, with electrodes arranged in multiple layers (first electrode, first dielectric, second electrode, second dielectric) stacked vertically. This dimensional change enables significantly increased capacitance per unit area by utilizing the vertical space rather than only horizontal plane, directly resolving the contradiction between achieving high capacitance and minimizing footprint.
2Productivity
If device density is increased to improve circuit integration, then the available footprint is reduced, but the space required for capacitor structures becomes insufficient
Solution Approach 1:
By forming capacitors in vertical trenches rather than planar configurations, the patent enables high-density integration. The trench structure occupies minimal horizontal footprint while providing sufficient capacitance through vertical stacking of electrodes and dielectrics. This allows more capacitor structures to be packed into the same die area, supporting higher device density without sacrificing capacitor performance.
Solution Approach 2:
The capacitor structure employs nested arrangement where the second electrode and second dielectric are positioned within the vertical space above the first electrode and first dielectric in the same trench. This nesting of multiple capacitor elements in a single vertical column maximizes the use of available vertical space, enabling multiple capacitance units to be integrated in the footprint of a single planar capacitor.
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
Techniques are provided herein for forming one or more MIM trench capacitors in the interconnect region above the device layer of an integrated circuit. In an example, the MIM trench capacitor(s) are formed within one of the upper interconnect layers of the interconnect region, and thus can have a relatively high height (e.g., greater than about 200 nm). An interconnect layer included in a stack of interconnect layers includes a MIM capacitor having a first electrode (206), a capacitor dielectric (210) on the first electrode, and a second electrode (212) on the capacitor dielectric. The MIM capacitor runs along the outside surface of a plurality of dielectric fins (204), which greatly increases the surface area of the capacitor within a relatively small plan footprint. The first and second electrodes may connect with one or more topside contacts (216, 218) and/or one or more buried conductive lines (220, 222).