MIMD Ray Tracing Device T&I Scheduling
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Solution Overview
Problem
Current ray tracing techniques face inefficiencies in computation and memory bandwidth requirements for 3D graphics, particularly in traversal and intersection tests, which hinder effective simulation of optical effects and photorealistic image production.
Innovation Solution
A ray tracing device employing MIMD-based T&I scheduling, with a ray receiving unit, scheduling unit, traversal/intersection test unit, and test result ordering unit, that prioritizes and allocates rays across multiple T&I pipelines for parallel processing, merging similar test results and calculating hit points efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple T&I pipelines are used for parallel processing, then computational throughput is improved, but device complexity increases due to buffer management and scheduling requirements
Solution Approach 1:
The system segments the ray tracing workload into multiple independent T&I pipelines, each capable of parallel processing. Rays are divided and distributed across multiple pipelines (e.g., Pipeline 0, Pipeline 1, etc.), allowing simultaneous traversal and intersection testing to occur in parallel, thereby increasing computational throughput while maintaining manageable complexity through modular architecture
Solution Approach 2:
A ray scheduling unit acts as an intermediary between the ray buffer and multiple T&I pipelines. This mediator allocates rays to appropriate pipelines based on scheduling criteria, manages buffer outputs in priority order, and coordinates the parallel processing across pipelines, thereby enabling high throughput without requiring complex direct management between all components
2Productivity
If priority-based buffer scheduling is implemented, then ray tracing efficiency is improved, but device complexity increases due to scheduling mechanisms
Solution Approach 1:
The system implements preliminary action by pre-assigning priorities to rays based on their frame identifier and processing requirements before they enter the T&I pipelines. The ray scheduling unit maintains a priority queue structure where rays are ordered by importance, ensuring that high-priority rays are processed first without requiring complex real-time scheduling decisions during execution
Solution Approach 2:
The scheduling mechanism is designed to be dynamic, allowing the ray scheduling unit to adaptively allocate rays to different pipelines based on current buffer states and priority levels. The system can dynamically adjust which pipeline receives which ray based on load balancing considerations and priority requirements, providing flexibility without excessive complexity
3Quantity of substance
If test results are re-arranged and merged, then memory utilization is improved, but processing time increases due to additional sorting operations
Solution Approach 1:
The test result ordering unit merges test results from multiple T&I pipelines by combining results with the same frame identifiers. Instead of maintaining separate sorted buffers for each pipeline, the system consolidates results, eliminating redundancy and optimizing memory utilization by storing only unique frame data across all pipelines
Solution Approach 2:
The system changes the organizational parameter of test results from pipeline-specific ordering to frame-based ordering. By re-arranging results according to frame identifiers rather than pipeline assignment, the system enables more efficient memory access patterns and better memory utilization while the merging process eliminates duplicate processing of identical frame data
Data Source
AI summary
Disclosed is a ray tracing device using MIMD based T&I scheduling, including: a ray receiving unit receiving a ray generated with respect to a specific frame according to a frame progress order and storing the received ray in a ray buffer; a ray scheduling unit allocating a ray provided by the ray buffer to one of a plurality of T&I pipelines, each of which including an input and output buffers; a traversal/intersection test performing unit performing a traversal/intersection test on an allocated ray in a parallel fashion by using each of the plurality of T&I pipelines and determining a triangle intersecting the allocated ray; and a test result ordering unit receiving information about the triangle from the plurality of T&I pipelines as a test result, storing the received test result in a test buffer, and re-arranging the received test result according to a frame progress order.