Multi-Voltage Domain Mimic Logic for Memory Wordline Decoding
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Solution Overview
Problem
In multi-voltage domain memory systems, device variations in the low voltage domain cause timing glitches that translate to significant issues in the high voltage domain, leading to unstable relationships between control signals, which can result in memory failure.
Innovation Solution
The implementation of multi-voltage domain control circuits that include decoding logic to generate a wordline and mimic logic to generate a dummy wordline, ensuring stable relationships between control signals by mimicking the decoding logic across both low and high voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multi-voltage domain memory is implemented with low voltage decoding logic and high voltage memory array, then power consumption is reduced, but device variations in low voltage domain cause timing glitches that lead to unstable control signals
Solution Approach 1:
The patent creates a copy of the decoding logic circuit that generates a dummy wordline mirroring the timing characteristics of the actual wordline. This copy circuit replicates the critical timing behavior without affecting power consumption, allowing the dummy wordline to be used for timing reference and stabilization of control signals across voltage domains.
Solution Approach 2:
The dummy wordline acts as an intermediary between the low voltage decoding logic and the high voltage memory array. It mediates the timing relationship by providing a reference signal that accounts for device variations in the low voltage domain, thereby stabilizing control signals without requiring changes to the power consumption structure.
2Speed
If devices operate faster in high voltage domain, then performance is improved, but timing glitches from low voltage domain translate to large timing glitches in high voltage domain
Solution Approach 1:
By creating a dummy wordline through copying the decoding logic, the patent captures the timing behavior of the low voltage domain devices. This copy allows measurement and compensation of timing variations without slowing down the actual high voltage domain operations, thus maintaining speed while improving timing precision.
Solution Approach 2:
The dummy wordline is generated in advance alongside the actual wordline, allowing timing relationships to be established before critical operations occur. This preliminary timing reference enables proper synchronization of control signals, preventing timing glitches from propagating to the high voltage domain.
3Loss of energy
If wordline decoding logic is placed in low voltage domain, then power consumption is reduced, but stable relationship between control signals cannot be maintained
Solution Approach 1:
The patent places a copy of the decoding logic in the low voltage domain that generates the dummy wordline. This copying approach maintains the power consumption benefits of low voltage operation while providing a stable timing reference that preserves the relationship between control signals across voltage domains.
Solution Approach 2:
The dummy wordline creates an equipotential timing reference that equalizes the timing relationship between low voltage decoding logic and high voltage memory array. By providing this reference, the patent maintains stable control signal relationships despite the voltage domain difference, effectively creating timing equivalence across domains.
Data Source
AI summary
Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.