MIMO Power Converter with Booster Circuit for High dl/dt Cores
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Solution Overview
Problem
Existing DC-DC power converters face challenges in providing efficient transient load response and scalable output voltage to multiple high dl/dt cores due to size constraints and parasitic elements, leading to signal delays and loop stability issues, as well as inefficiencies at low load conditions affecting battery life.
Innovation Solution
A dual Multiple-Inductor Multiple-Output (MIMO) system with a booster circuit that bypasses parasitic networks, using a single set of shared inductors and a symmetrical or asymmetrical multi-phase buck converter to supply multiple output voltages and provide peak boost energy to individual cores, minimizing parasitic effects and optimizing efficiency across all load ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power converter supplies multiple cores with long routing traces, then device complexity is reduced, but parasitic elements increase causing signal delays and loop stability challenges
Solution Approach 1:
The patent divides the power delivery system into multiple independent power converters, each serving specific cores. This segmentation eliminates long routing traces by placing power converters close to core loads, reducing parasitic elements while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The patent transitions from a single centralized power converter to a multi-dimensional distributed power converter architecture. Each core or group of cores has its own dedicated power converter, creating a spatial distribution that reduces routing trace length and parasitic effects while maintaining system manageability
2Power
If power converter operating efficiency is optimized for higher load ranges, then high load performance improves, but low load efficiency deteriorates affecting battery life
Solution Approach 1:
The patent implements different operating modes for different phases of the power converter. Some phases operate in valley mode while others operate in peak mode, allowing each phase to be optimized for its specific operating conditions. This local optimization enables efficient operation across both high and low load ranges
Solution Approach 2:
The patent employs dynamic operating mode switching where power converter phases can transition between valley mode and peak mode operation based on load conditions. This dynamic adaptation allows the system to maintain high efficiency across varying load ranges, preventing energy waste during low load periods while maintaining performance during high load periods
3Loss of energy
If cores enter and exit sleep mode rapidly to reduce power consumption, then power saving improves, but transient load response requirements increase
Solution Approach 1:
The patent positions power converters in close proximity to core loads and configures them to rapidly respond to transient current demands. This preliminary positioning and configuration enables the power converters to immediately supply current during wake-up events, supporting rapid sleep mode transitions without compromising transient response
Solution Approach 2:
The patent introduces dedicated power converters as intermediary components between the power source and cores. These intermediary converters are specifically configured to handle transient load demands during core wake-up events, enabling rapid sleep mode transitions while maintaining stable power delivery
4Adaptability or versatility
If output voltage is scaled per core to optimize performance, then adaptability improves, but device complexity and routing requirements increase
Solution Approach 1:
The patent divides the power conversion function into multiple independent converters, each capable of providing scaled output voltages to specific cores. This segmentation enables per-core voltage scaling without requiring complex centralized control, as each converter independently manages its output voltage based on the requirements of its associated core
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances transient load performance, reduces component count and PCB footprint, and improves scalability and efficiency by providing point-of-load support for high dl/dt cores, minimizing battery drain and optimizing battery life through centralized resource management.
Implementation Method 1
A dual Multiple-Inductor Multiple-Output (MIMO) system with a booster circuit that bypasses parasitic networks, using a single set of shared inductors
Implementation Method 2
a main Multiple-Inductor Multiple-Output (MIMO) switching converter, configured as a primary power source, to supply several different output voltages
Data Source
AI summary
It is an object of one or more embodiments of the present disclosure to provide a Multiple-Inductor Multiple-Output (MIMO) switching converter to supply several different output voltages. The combination of this MIMO converter with a booster circuit supplies one or more individual cores with current that bypasses the parasitic network. The booster circuit has a wider bandwidth or a faster response when compared to the main MIMO switching converter. The MIMO booster circuit can supply a number of cores with only a single set of shared inductors. The main advantages include a lower component count and a reduced printed circuit board footprint to support multiple cores in a Multiple-Inductor Multiple-Output. The present disclosure makes use of the low duty-cycle of the power peaks and the low statistical likelihood of these peaks occurring for all cores simultaneously.