MIMO Carrier Aggregation Receiver Reuse Architecture
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Solution Overview
Problem
Current wireless communication devices face challenges in maximizing battery life and reducing size and cost while maintaining high downlink throughput, particularly in MIMO carrier aggregation systems, which often require additional circuitry and power consumption.
Innovation Solution
The implementation of a multiple-input and multiple-output (MIMO) carrier aggregation receiver reuse architecture that reuses existing receiver paths, eliminating the need for a power splitter and external low noise amplifier, and utilizing shared synthesizers to reduce power consumption and die area, allowing for 4Rx multiple-input and multiple-output communications using multiple antennas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional MIMO carrier aggregation receiver architecture is used, then downlink throughput is improved, but power consumption increases and device size increases
Solution Approach 1:
The patent implements multi-functionality by enabling the same receiver architecture to handle both carrier aggregation operations and MIMO operations. The receiver chip can reuse existing carrier aggregation receiver paths for MIMO communications, eliminating the need for separate dedicated MIMO receiver paths and thereby reducing power consumption while maintaining downlink throughput capability.
Solution Approach 2:
The patent merges the carrier aggregation receiver functionality with MIMO receiver functionality into a unified architecture. By combining these functions into a single receiver chip that shares common components (such as low noise amplifiers, filters, and processing paths), the system achieves both high downlink throughput and reduced power consumption compared to separate dedicated architectures.
2Productivity
If traditional MIMO carrier aggregation receiver architecture is used, then downlink throughput is improved, but device size increases
Solution Approach 1:
The receiver chip is designed with multi-functionality to perform both carrier aggregation and MIMO operations using the same physical and logical resources. This eliminates the need for separate dedicated MIMO receiver circuits, thereby reducing the overall die area while maintaining the capability to achieve high downlink throughput through MIMO carrier aggregation.
Solution Approach 2:
The patent combines carrier aggregation receiver paths with MIMO receiver paths into a unified integrated circuit architecture. By merging these functions and sharing common components such as low noise amplifiers, filters, and signal processing units, the system reduces the total die area required while preserving high downlink throughput performance.
3Productivity
If additional circuitry is added for MIMO carrier aggregation, then downlink throughput is improved, but cost increases
Solution Approach 1:
The receiver chip employs multi-functionality where the same circuitry serves dual purposes: carrier aggregation operations and MIMO operations. This eliminates the need for additional dedicated MIMO receiver circuitry, thereby reducing manufacturing cost while maintaining the capability to deliver high downlink throughput through MIMO carrier aggregation.
Solution Approach 2:
The patent merges carrier aggregation and MIMO receiver functionalities into a single integrated chip design that shares common components. This consolidation reduces the total number of circuitry elements required, simplifying manufacturing processes and reducing cost while preserving high downlink throughput capability.
4Reliability
If power splitter and external low noise amplifier are used, then signal reception is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent extracts and eliminates the need for separate power splitters and external low noise amplifiers by integrating these functions directly into the receiver chip architecture. The receiver chip incorporates integrated low noise amplifiers and signal processing capabilities that perform the same functions without requiring separate external components, thereby reducing device complexity while maintaining signal reception performance.
Solution Approach 2:
The patent combines the functions of power splitting and low noise amplification into the integrated receiver chip architecture. By merging these functions into a single integrated design with shared components, the system achieves reliable signal reception while reducing overall device complexity compared to separate discrete component implementations.
Data Source
AI summary
A wireless communication device configured for receiving a wireless multiple-input and multiple-output signal. The wireless communication device includes a first multiple-input and multiple-output carrier aggregation receiver reuse architecture. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a first antenna, a second antenna and a transceiver chip. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a first carrier aggregation receiver path. The wireless communication device also includes a second multiple-input and multiple-output carrier aggregation receiver reuse architecture. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a third antenna, a fourth antenna and a receiver chip. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a second carrier aggregation receiver path.