MIMO DAC Clock Phase Alignment for Spur Cross-Coupling Reduction
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Solution Overview
Problem
Clock spurs generated by clock signals in digital-to-analog converters (DACs) of transmission chains cause noise that cross-couple to other chains, leading to difficult-to-filter spurs and impacting output waveforms in beamforming applications.
Innovation Solution
Adjusting the phases of clock and data paths in transmission chains using a controller to reduce cross-coupling of spurs, employing separate reset phases for clock dividers and fractional delay filters to compensate for phase adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If clock signals are used to synchronize transmission chains for beamforming, then synchronous operations are enabled, but clock spurs are generated that cross-couple to other chains causing noise
Solution Approach 1:
The patent applies preliminary anti-action by pre-adjusting the phase of clock signals and data paths before beamforming operations to specifically counteract and reduce clock spur cross-coupling. The controller modifies clock phases and data path phases in advance to cancel out the harmful spur effects that would otherwise occur during synchronous transmission chain operation.
2Object-generated harmful factors
If clock phases are adjusted to reduce spur cross-coupling, then spur levels are reduced, but output waveforms may be affected
Solution Approach 1:
The patent applies parameter changes by simultaneously adjusting multiple parameters including clock phase, data path phase, and fractional delay filter settings. The controller modifies these parameters in a coordinated manner to reduce spur levels while maintaining output waveform accuracy through compensatory phase adjustments in the data paths.
Solution Approach 2:
The patent employs feedback mechanisms where the controller monitors the effects of phase adjustments on both spur levels and output waveforms, then iteratively refines the clock and data path phases to achieve optimal performance that reduces spurs while preserving waveform integrity.
3Measurement precision
If separate reset phases are used for clock dividers and fractional delay filters, then phase compensation is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by using a single controller to manage multiple functions including clock phase adjustment, data path phase adjustment, and fractional delay filter control. This multi-functional approach enables precise phase compensation across different transmission chains while avoiding the complexity of separate dedicated control circuits for each function.
Data Source
AI summary
Certain aspects of the present disclosure provide techniques and apparatus for signal transmission. An example apparatus generally includes: a first transmission chain including a first clock generator and a first digital-to-analog converter (DAC), an output of the first clock generator being coupled to a clock input of the first DAC, wherein the first transmission chain further includes a first digital data path coupled to an input of the first DAC; a second transmission chain including a second clock generator and a second DAC, an output of the second clock generator being coupled to a clock input of the second DAC, wherein the second transmission chain further includes a second digital data path coupled to an input of the second DAC; and a controller configured to set a first data phase associated with the first digital data path based on a first clock phase associated with the first clock generator.