MIMO FIFO Buffer Circuit Parallel Readout Architecture
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Solution Overview
Problem
Digital circuit designs face inefficiencies in data processing due to the limitations of single-input single-output (SISO) FIFO buffers, which restrict the ability to read out data in parallel, leading to increased latency and reduced processing speeds.
Innovation Solution
A multi-input multi-output (MIMO) FIFO buffer circuit is introduced, featuring a storage array with multiple storage blocks and an internal pointer generator that allows for simultaneous reading of data flits based on an internal pointer increment value, enabling efficient data processing across multiple storage blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a SISO FIFO buffer is used, then the device complexity is low, but the data processing speed is slow and latency is high
Solution Approach 1:
The FIFO buffer is segmented into multiple storage blocks (first storage block, second storage block, etc.), each capable of independent read/write operations. This segmentation enables parallel data processing across multiple blocks, significantly improving data processing speed while maintaining manageable complexity through modular architecture
Solution Approach 2:
The buffer structure transitions from a single-input single-output (SISO) linear architecture to a multi-input multi-output (MIMO) multi-dimensional architecture with multiple storage blocks. This dimensional expansion allows simultaneous read/write operations on different blocks, enhancing processing speed without proportionally increasing complexity
2Loss of time
If a SISO FIFO buffer is used, then the device complexity is low, but the latency is high
Solution Approach 1:
Data is pre-loaded into multiple storage blocks in advance, and multiple read pointers (first read pointer, second read pointer, etc.) are prepared to access different blocks simultaneously. This preliminary preparation enables concurrent read operations, reducing data latency without requiring complex dynamic arbitration logic
Solution Approach 2:
The buffer is divided into multiple storage blocks that can be accessed in parallel by different read pointers. This segmentation allows simultaneous data retrieval from multiple blocks, significantly reducing the time required to fetch multiple data flits compared to sequential access in a SISO buffer
3Productivity
If a MIMO FIFO buffer with multiple storage blocks is used, then the data processing speed is improved, but the device complexity increases
Solution Approach 1:
The buffer is segmented into multiple storage blocks with dedicated write pointers and read pointers for each block. This segmentation enables parallel write and read operations across blocks, increasing data throughput while maintaining systematic control through modular pointer management
Solution Approach 2:
Each storage block is designed with universal functionality to handle both read and write operations independently. The control logic uses standardized pointer increment mechanisms and data flit transfer protocols across all blocks, allowing the system to achieve high throughput through parallelism without requiring complex block-specific control circuits
4Productivity
If concurrent read operations are performed on multiple storage blocks, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The control logic is segmented into independent pointer management units for each storage block, with each read pointer (first read pointer, second read pointer, etc.) independently controlling its associated block. This segmentation allows concurrent read operations without requiring complex arbitration logic, as each block operates autonomously under its own pointer control
Solution Approach 2:
Each storage block autonomously manages its own read/write operations through dedicated pointers and control signals. The blocks self-coordinate through standardized data flit transfer protocols without requiring centralized arbitration, enabling concurrent processing while keeping control logic complexity manageable through decentralized autonomous operation
Data Source
AI summary
Disclosed is a MIMO FIFO buffer circuit that reads out data flits at once as many as an internal pointer increment value. The MIMO FIFO buffer circuit includes a MIMO FIFO storage array including ‘Y’ storage blocks, and an internal pointer generator that generates an internal pointer based on an internal pointer increment value indicating the number of data flits to read out at once from among ‘K×X’ data flits stored in K storage blocks out of the ‘Y’ storage blocks. Each of the ‘Y’ and the ‘K’ is a natural number, and the ‘K’ is equal to or less than the ‘Y’, and each of the ‘K’ storage blocks stores ‘X’ data flits.