MIMO HARQ Receiver Symbol Combining for Lower Error Rates

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Solution Overview

Problem

MIMO IR HARQ systems often use sub-optimal receiver structures, leading to increased bit- and symbol-error rates, reduced application quality, and increased system latency, necessitating improved decoding strategies and symbol vector-level combining techniques.

Innovation Solution

The implementation of a symbol vector-level combining technique in MIMO IR HARQ systems, where information bits are encoded into a mother code, transmitted, and retransmitted with incremental redundancy, allowing for iterative decoding and error correction at the receiver, effectively lowering the error-floor and increasing information rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sub-optimal receiver structures are used in MIMO IR HARQ systems, then device complexity is reduced, but bit-error rate and symbol-error rate increase

Engineering Contradiction:
Improvebit-error rateVSAvoidreceiver structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The receiver structure is segmented into distinct functional modules: MIMO equalizer, symbol vector combiner, and decoder. This segmentation allows each module to perform a specific optimization function while maintaining overall system manageability and near-optimal performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary encoding and interleaving at the transmitter to create a mother code, and prepares symbol vectors for combining before reception. This preliminary structuring enables the receiver to achieve near-optimal error rates through systematic combining rather than complex real-time processing

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If sub-optimal receiver structures are used in MIMO IR HARQ systems, then device complexity is reduced, but system latency increases

Engineering Contradiction:
Improvesystem latencyVSAvoidreceiver structure complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

By segmenting the receiver into specialized modules, each operation (equalization, combining, decoding) can be optimized for speed within its function, reducing overall processing latency compared to monolithic sub-optimal structures

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The symbol vector combiner merges information from multiple transmissions and antennas in a coordinated manner, efficiently utilizing redundant information to reduce the number of retransmissions needed and thereby reducing system latency

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If iterative transmission and decoding is implemented, then bit-error rate decreases, but computational complexity increases

Engineering Contradiction:
Improvesymbol-error rateVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The iterative decoding process is segmented into discrete passes through the equalizer and combiner modules, allowing the system to achieve near-optimal error rates through multiple refined processing stages rather than a single complex operation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs a limited number of iterative passes (excessive enough to achieve near-optimal performance but not unlimited) through the combining and decoding modules, balancing computational complexity with error rate reduction

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8271861B2Symbol vector-level combining receiver for incremental redundancy HARQ with MIMO
Publication Date: 2012.09.18 NXP USA INC
  • US8271861B2 patent drawing
  • US8271861B2 patent drawing
  • US8271861B2 patent drawing

AI summary

Techniques are provided for transmitting and receiving a mother code in an incremental redundancy hybrid automatic repeat-request protocol. A set of information bits corresponding to a message is encoded and interleaved to produce the mother code. Each bit position of the mother code is mapped to an output symbol, and each output symbol is mapped to an antenna for transmission. One or more transmissions are performed, where each transmission includes puncturing the mother code by selecting one or more symbols from the output symbols, and transmitting each symbol in the one or more symbols on an antenna corresponding to that symbol. The mother code is decoded, in part, by determining combinable bits contained within a set of received symbols and computing one or more log-likelihood ratio values corresponding to each symbol in the set of received symbols.