MIMO IQ Path Synchronization Circuit Using Preliminary Sync Signals
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Solution Overview
Problem
MIMO wireless systems face challenges in maintaining synchronization between multiple transmitters and receivers due to glitches and differing initial operating conditions in timing circuits, leading to timing problems and inefficiencies.
Innovation Solution
The implementation of a circuit that generates sync enable signals for each flip-flop divider, allowing the MIMO wireless device to produce synchronized IQ paths while ignoring inherent glitches or initial operating conditions of individual components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transmitters and receivers are used simultaneously in MIMO systems, then data rate is increased, but power consumption increases and synchronization becomes difficult to maintain
Solution Approach 1:
The patent applies preliminary action by generating sync enable signals in advance based on even edges of the clock signal before the IQ paths are generated. This preliminary synchronization signal ensures that all flip-flop dividers start from a known synchronized state, preventing timing issues that would otherwise require complex real-time synchronization mechanisms.
Solution Approach 2:
The patent introduces an intermediary sync enable signal that mediates between the clock signal and the IQ path generation in multiple transmitters and receivers. This intermediary signal acts as a common reference that coordinates all timing circuits, allowing them to operate independently yet remain synchronized without direct communication between them.
2Ease of operation
If flip-flop dividers with internal memory elements are used in timing circuits, then IQ path generation is enabled, but synchronization between dividers becomes unstable due to different initial memory states
Solution Approach 1:
The patent applies preliminary action by generating sync enable signals in advance based on even edges of the clock signal before the IQ paths are generated. This preliminary synchronization signal ensures that all flip-flop dividers start from a known synchronized state, preventing timing issues that would otherwise require complex real-time synchronization mechanisms.
Solution Approach 2:
The patent creates equipotentiality by providing all flip-flop dividers with the same sync enable signal derived from the same clock source. This ensures that all dividers operate under identical timing conditions regardless of their individual initial memory states, making them functionally equivalent in terms of synchronization.
3Reliability
If additional synchronization components and control mechanisms are added to maintain coordination between TX and RX chains, then synchronization is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by using a single clock signal source that serves multiple functions: it directly clocks the dividers, provides the basis for sync enable signals, and implicitly synchronizes all IQ paths. This multi-functional approach eliminates the need for separate synchronization circuits for each transmitter or receiver chain.
Solution Approach 2:
The patent applies preliminary action by generating sync enable signals in advance based on even edges of the clock signal before the IQ paths are generated. This preliminary synchronization signal ensures that all flip-flop dividers start from a known synchronized state, preventing timing issues that would otherwise require complex real-time synchronization mechanisms.
Data Source
AI summary
Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first IQ path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second IQ path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.