MIMO Receiver Joint Detection with Parallel Soft-Bit Processing
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Solution Overview
Problem
In MIMO communication systems, existing joint detection methods require significant computational resources to generate soft bits, especially for higher-order modulation constellations, and are not efficiently implementable in hardware due to high complexity and non-parallelizable processing requirements.
Innovation Solution
The implementation of 'fast joint detection' (FJD) in wireless communication receivers, which reduces computational complexity by using dedicated signal processing hardware and parallelizable algorithms to generate soft bits, specifically by computing likelihood metrics for symbol combinations and storing best metrics for bit positions, facilitating efficient turbo decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional joint detection methods are used to generate soft bits for MIMO data streams, then decoding accuracy is maintained, but computational complexity increases significantly and processing time is excessive
Solution Approach 1:
The patent segments the joint detection process into distinct functional modules: S-matrix computation, combined symbol vector generation, metric calculation, and soft bit extraction. Each module operates independently and can be processed in parallel, reducing overall computational complexity while maintaining decoding accuracy.
Solution Approach 2:
The patent performs preliminary computations of the S-matrix and combined symbol vector before the actual metric evaluation and soft bit generation. These pre-computed values are stored and reused across multiple symbol vectors, eliminating redundant calculations and significantly reducing processing time for higher-order modulation constellations.
2Productivity
If conventional joint detection algorithms are implemented, then reliable soft bits are generated, but the processing cannot be efficiently parallelized in hardware
Solution Approach 1:
The detection algorithm is divided into independent computational stages that can be executed in parallel hardware pipelines. Each stage processes different aspects of the detection problem (S-matrix, symbol vectors, metrics, soft bits) separately, enabling efficient VLSI implementation with multiple parallel processing units.
Solution Approach 2:
The patent designs a universal processing framework that can handle multiple modulation schemes (QPSK, 16QAM, 64QAM, 256QAM) using the same hardware architecture. The S-matrix and combined symbol vector computations are stream-independent and can be reused across different modulation types, making the hardware implementation versatile and efficient.
3Measurement precision
If full joint detection processing is performed for all symbol combinations, then accurate soft bits are obtained, but processing time exceeds allowable limits
Solution Approach 1:
The S-matrix and combined symbol vector are computed in advance and stored for reuse across multiple symbol vectors. This preliminary action eliminates redundant calculations while maintaining the accuracy required for reliable soft bit generation, significantly reducing processing time within allowable limits.
Solution Approach 2:
The patent reuses the S-matrix across consecutive symbol vectors, especially in HSDPA where the same S-matrix estimate is used over a whole slot. This copying approach maintains detection accuracy while dramatically reducing the computational burden of repeated full joint detection processing.
Data Source
AI summary
According to one aspect of the teachings presented in this document, a wireless communication receiver implements a form of joint detection that is referred to as “fast joint detection” (FJD). A receiver that is specially adapted to carry out FJD processing provides an advantageous approach to joint detection processing wherein the number of computations needed to produce reliable soft bits, for subsequent turbo decoding and/or other processing, is significantly reduced. Further, the algorithms used in the implementation of FJD processing are particularly well suited for parallelization in dedicated signal processing hardware. Thus, while FJD processing is well implemented via programmable digital processors, it also suits applications where high-speed, dedicated signal processing hardware is needed or desired.