MIMO Signal Mapping With LDPC Bit-Length Adjustment

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Solution Overview

Problem

Implementing the MIMO scheme with LDPC coding poses challenges due to bit length mismatches between different signal streams.

Innovation Solution

A data processing scheme that includes an encoding step for generating N-bit codewords, a mapping step for creating complex signals, and a bit length adjustment step to ensure that the bit length of the second bit sequence is a multiple of the sum of the bits used for the first and second complex signals, facilitating the MIMO scheme's implementation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC coding is applied to MIMO scheme, then error correction capability is improved, but bit length mismatch occurs between different signal streams

Engineering Contradiction:
Improveerror correction capabilityVSAvoidbit length mismatch
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the bit length parameter of the second bit sequence by adding zero bits to make it a multiple of (X+Y). This parameter adjustment resolves the bit length mismatch between the first bit sequence (N bits from LDPC coding) and the second bit sequence (requiring multiple of X+Y bits for complex signal mapping), enabling proper MIMO signal generation while maintaining LDPC error correction capability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs bit length adjustment (adding zero bits) to the second bit sequence before the mapping step. This preliminary action ensures that the bit length compatibility requirement is satisfied in advance, allowing the MIMO scheme to proceed without bit length mismatch issues between the coded bit sequences and the complex signal mapping requirements

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10819464B2Data processing method, precoding method, and communication device
Publication Date: 2020.10.27 SUN PATENT TRUST
  • US10819464B2 patent drawing
  • US10819464B2 patent drawing
  • US10819464B2 patent drawing

AI summary

An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s1 and a second complex signal s2 with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s1, and Y indicates the number of bits used to generate the second complex signal s2. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved.