Mini Field Plate T-Gate Structure for Low-Capacitance HEMTs

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Solution Overview

Problem

High electron mobility transistors (HEMTs) face challenges with high electric fields at the drain edge of the gate leading to breakdown and increased dynamic on-resistance during high voltage switching, which is exacerbated by field plate structures that increase capacitance, inhibiting high-frequency operation.

Innovation Solution

A mini field plate structure is introduced, with a tri-layer gate design that includes a gate foot, neck, and head, where the mini field plates are positioned at the gate edges to reduce peak electric fields and parasitic capacitance, while maintaining mechanical strength and low gate capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If field plate structures are used to reduce maximum electric field intensity, then breakdown voltage is improved, but gate capacitance increases adversely affecting cutoff frequency and maximum frequency

Engineering Contradiction:
Improvebreakdown voltageVSAvoidcutoff frequency and maximum frequency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The gate structure is segmented into three distinct layers: gate foot, gate neck, and gate head. This segmentation allows each portion to serve specific functions - the gate foot provides mechanical support, the gate neck controls the channel, and the gate head forms the field plate. By dividing the gate into functional segments, the patent achieves breakdown voltage enhancement through the field plate while minimizing capacitance increase compared to a conventional unified gate structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the gate structure are given different properties and dimensions. The gate foot has a first width, the gate neck has a second width narrower than the gate foot, and the gate head has a third width wider than the gate neck. This local differentiation allows the field plate (gate head) to extend over the drain region to suppress electric fields locally, while the narrower gate neck minimizes capacitance, thus resolving the contradiction between breakdown voltage and frequency performance.

Inventive Principle:
Principle #3Local quality

2Reliability

If conformal gates are used to the field plate dielectric, then field plate functionality is achieved, but capacitance increases higher than necessary

Engineering Contradiction:
Improvefield plate functionalityVSAvoidcapacitance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The gate structure implements local quality by having different widths at different positions. The gate neck portion is specifically designed with a narrower width compared to both the gate foot and gate head. This localized narrowing reduces the capacitance between the gate and the underlying structures in the critical region, while still maintaining the field plate functionality through the gate head extension, thus resolving the capacitance issue with conformal gates.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

By segmenting the gate into foot, neck, and head portions with different dimensions, the patent optimizes each segment's contribution to overall performance. The gate neck segment specifically addresses the capacitance issue by being narrower, while the gate head segment maintains field plate functionality. This segmentation approach achieves field plate functionality with minimized necessary capacitance.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11764271B2Miniature field plate T-gate and method of fabricating the same
Publication Date: 2023.09.19 HRL LAB
  • US11764271B2 patent drawing
  • US11764271B2 patent drawing
  • US11764271B2 patent drawing

AI summary

A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.