Mini LED Driving Backplane Planarization for Flat Wiring and Welding

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Solution Overview

Problem

The existing Mini LED driving backplane designs face challenges such as wire breakage and poor welding due to height differences and uneven surfaces, which affect the display quality and reliability.

Innovation Solution

The proposed driving backplane structure includes a base substrate with a first conductive layer, a first planarization layer outside the conductive layer pattern, a second planarization layer overlapping the first conductive layer, and a second conductive layer on the second planarization layer, where the orthographic projection of the first conductive layer partially overlaps with the second conductive layer, and the planarization layers help in uniform thickness and insulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional Mini LED driving backplane structure is used, then the device can be manufactured, but height differences and uneven surfaces cause wire breakage and poor welding

Engineering Contradiction:
Improvewelding qualityVSAvoidsurface flatness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a planarization layer before the second conductive layer to pre-compensate for height differences. This planarization layer is deposited to fill valleys and create a flat surface, preventing wire breakage and ensuring good welding quality in advance before subsequent manufacturing steps occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The planarization layer acts as an intermediary between the first conductive layer and the second conductive layer. It mediates the height differences created by the patterned first conductive layer, providing a uniform intermediate surface that enables reliable wire formation and welding without direct contact between the uneven first conductive layer and the second conductive layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the first conductive layer is made thicker to reduce resistance, then electrical performance improves, but height differences increase causing wire breakage

Engineering Contradiction:
Improveelectrical conductivityVSAvoidsurface height uniformity
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The planarization layer is formed in advance to compensate for the height differences created by the thick first conductive layer. By depositing this intermediate layer before forming the second conductive layer, the patent ensures that the electrical performance benefit of the thick first conductive layer is maintained while the surface flatness problem is pre-corrected.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If multiple pattern processes are used to form conductive layers with different thicknesses, then electrical performance improves, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the thickness control function into a single planarization step rather than requiring multiple separate pattern processes. The planarization layer is deposited uniformly and then patterned once to create the desired thickness variations, combining what would otherwise require multiple fabrication steps into one integrated process.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12265296B2Driving backplane, manufacturing method thereof and display panel
Publication Date: 2025.04.01 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US12265296B2 patent drawing
  • US12265296B2 patent drawing
  • US12265296B2 patent drawing

AI summary

An embodiment of the present disclosure provides a driving backplane, which includes: a base substrate; a first conductive layer on the base substrate; a first planarization layer on the base substrate and in a region outside a pattern of the first conductive layer; a second planarization layer on a side of the first conductive layer and the first planarization layer distal to the base substrate; and a second conductive layer on a side of the second planarization layer distal to the base substrate, wherein an orthographic projection of the first conductive layer on the base substrate partially overlaps with an orthographic projection of the second conductive layer on the base substrate.