Miniaturized MOSFET Structure With Self-Aligned Source/Drain Contacts
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Solution Overview
Problem
The challenge in shrinking the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) is hindered by photolithographic misalignment tolerances, which limit the minimum feature size and prevent the creation of smaller source/drain lengths and contact holes, essential for integrating more transistors on a silicon wafer while reducing leakage currents and power consumption.
Innovation Solution
A method that uses a single photolithography process to control the length of the conductive region between the gate and isolation regions, and self-alignment technology to define contact holes independently of photolithography, allowing for precise control of source and drain dimensions without misalignment tolerances, enabling contact holes smaller than the minimum feature size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithographic masking technology is used to define transistor dimensions, then manufacturing capability is improved, but misalignment tolerance prevents precise control of source/drain length
Solution Approach 1:
The patent introduces dummy gates as intermediary structures that serve as alignment references during photolithography. These dummy gates are positioned adjacent to the active gate and used as masking references to define the source and drain regions, thereby mediating between the photolithography process capabilities and the required dimensional precision.
Solution Approach 2:
The patent performs preliminary formation of dummy gates and isolation structures before defining the active source/drain regions. This preliminary action establishes fixed reference structures that guide subsequent photolithography steps, ensuring that critical dimensions are determined by pre-formed structures rather than by alignment between multiple photolithography steps.
2Device complexity
If photolithographic masking is used to create contact holes, then manufacturing process is simplified, but minimum feature size is limited by misalignment tolerance
Solution Approach 1:
The patent uses self-aligned spacer structures as intermediaries to define contact hole positions and dimensions. These spacers are formed by depositing conformal layers on the dummy gates and isolation structures, automatically positioning contact holes with precision determined by spacer thickness rather than photolithographic alignment.
Solution Approach 2:
The patent replaces photolithographic mechanical alignment with a self-aligned deposition process. Instead of using photolithography to mechanically align contact hole openings with source/drain regions, the method uses conformal film deposition that automatically aligns contact holes to the pre-formed dummy structures, eliminating misalignment tolerance issues.
3Productivity
If transistor dimensions are shrunk to increase integration density, then number of transistors per area is improved, but photolithographic misalignment tolerance prevents further shrinkage
Solution Approach 1:
The patent introduces dummy gates and self-aligned spacers as intermediary structures that decouple the photolithography resolution limit from the final transistor dimensional precision. These intermediaries allow critical dimensions to be defined by deposition thickness control rather than photolithographic printing resolution, enabling feature sizes smaller than the photolithographic minimum.
Solution Approach 2:
The patent transitions from defining dimensions in the planar photolithography dimension to defining dimensions through vertical film thickness. By using conformal deposition to create spacers whose thickness determines horizontal feature dimensions, the method exploits the vertical dimension (film thickness control) to achieve precision in the horizontal dimension (feature size).
Data Source
AI summary
A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.