Miniaturized MOSFET Structure With Self-Aligned Source/Drain Control
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Solution Overview
Problem
The challenge in miniaturizing metal-oxide-semiconductor field-effect transistors (MOSFETs) lies in the inability to control the precise dimensions of source/drain lengths and contact openings due to photolithographic misalignment tolerances, which limits the shrinking of transistor size and integration density on silicon wafers.
Innovation Solution
A method is developed to precisely control the lengths of source/drain regions and contact holes by using a combination of photolithography processes, where the length of the conductive region is controlled by a single photolithography process configured to define the gate structure, and contact holes are formed independently of photolithography, allowing for dimensions as small as the minimum feature size without adding misalignment tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithographic masking technology is used to define source/drain regions and contact holes, then manufacturing process is simplified, but manufacturing precision deteriorates due to misalignment tolerance
Solution Approach 1:
The patent segments the definition process of source/drain regions and contact holes from the photolithographic gate patterning process. By using separate formation methods (such as spacer-based self-alignment or direct lithography) for source/drain regions and contact holes, the invention eliminates the cumulative misalignment errors that would occur if all features were defined in a single photolithography step, thereby improving manufacturing precision while maintaining process simplicity
Solution Approach 2:
The patent introduces spacer structures as intermediary elements between the gate electrode and source/drain regions. These spacers serve as self-aligned masks that automatically define the source/drain region boundaries with high precision, eliminating the need for separate photolithographic alignment steps and thus resolving the contradiction between manufacturing simplicity and precision
2Device complexity
If photolithographic masking technology is used to define contact holes, then process complexity is reduced, but contact hole dimension precision deteriorates
Solution Approach 1:
The patent implements self-aligned spacer formation where the spacer structures automatically define the contact hole positions and dimensions based on the gate electrode geometry. This self-service mechanism eliminates the need for separate photolithographic alignment steps for contact holes, achieving high dimension precision without increasing process complexity
Solution Approach 2:
The patent performs preliminary formation of spacer structures that pre-define the contact hole boundaries before actual contact hole etching. This preliminary action ensures that contact hole dimensions are precisely controlled by the spacer thickness rather than by subsequent photolithographic alignment, resolving the precision-complexity contradiction
3Productivity
If transistor dimensions are shrunk to increase integration density, then productivity is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent replaces the mechanical photolithographic alignment system with a self-aligned spacer formation mechanism. This substitution uses conformal film deposition and anisotropic etching processes that inherently provide sub-10nm precision, enabling transistor dimension shrinkage for higher integration density while maintaining or improving manufacturing precision
Solution Approach 2:
The patent changes the controlling parameter for feature size from photolithographic wavelength and alignment tolerance to thin film deposition thickness. By using atomic layer deposition or chemical vapor deposition to form spacers with precisely controlled thicknesses in the sub-10nm range, the invention enables continued transistor scaling while maintaining manufacturing precision
Data Source
AI summary
A transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is next to the first conductive region. A length of the first conductive region between the gate structure and the first isolation is controlled by a single photolithography process which is originally configured to define the length of the gate structure.