Minimizing Wander in Asynchronous Mapping Systems

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Solution Overview

Problem

Conventional methods for making justification decisions in asynchronous mapping systems introduce unwanted wander in the regenerated egress client clock due to sequential oscillations of the FIFO fill level, which can be cumulative across intermediate nodes.

Innovation Solution

The solution involves minimizing the effect of these oscillations by averaging multiple samples of the fill level over time or taking samples at non-uniformly spaced intervals, rather than fixed intervals, to make more accurate justification decisions and reduce wander generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If fixed interval sampling is used for justification decisions, then the system operation is simple, but sequential oscillations of FIFO fill level cause unwanted wander in the regenerated egress client clock

Engineering Contradiction:
Improvesystem operation simplicityVSAvoidclock signal stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent changes the sampling parameters by using non-uniformly spaced time intervals instead of fixed intervals. This modifies the sampling methodology to avoid the sequential oscillations that occur with regular sampling, thereby reducing unwanted wander in the regenerated clock signal while maintaining system operability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary filtering or processing to the fill level samples before making justification decisions. By pre-processing the samples (such as averaging multiple samples or applying a filter), the system prepares more accurate data for decision-making, which reduces the impact of oscillations and improves clock stability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple samples are averaged or non-uniform intervals are used, then wander generation is minimized, but the device complexity increases

Engineering Contradiction:
Improveclock signal stabilityVSAvoidjustification control logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the sampling process into multiple discrete samples taken at different non-uniform intervals. By dividing the single complex sampling operation into multiple simpler sample operations, the system achieves better clock stability through diversified sampling points without requiring a completely new complex control architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary processing stage that receives multiple fill level samples and produces a single justification decision. This intermediary layer (which may include averaging logic or filter circuits) absorbs the complexity, allowing the rest of the system to remain relatively simple while still achieving the benefit of reduced wander generation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If conventional justification decisions are made at fixed intervals, then the processing speed is high, but measurement precision of fill level is insufficient leading to wander

Engineering Contradiction:
Improveprocessing speedVSAvoidfill level measurement accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent makes the sampling intervals dynamic rather than static. By adjusting the time intervals between samples based on system conditions or using predetermined non-uniform patterns, the system captures fill level variations more accurately without significantly reducing the overall processing speed, thereby improving measurement precision while maintaining operational efficiency.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9225446B2Methods and apparatus for minimizing wander generation in constant bit rate asynchronously mapped digital transport systems
Publication Date: 2015.12.29 INFINERA CORP
  • US9225446B2 patent drawing
  • US9225446B2 patent drawing
  • US9225446B2 patent drawing

AI summary

A client receive circuit receives client data from a network, decodes the client data and stores the client data within the memory. A frame transmit circuit is provided that includes a justification control logic and a framer and a justification control logic is provided that 1) determines each of a plurality of fill levels and 2) determines an average of the plurality of fill levels. The framer has circuitry to generate a wrapper including a justification opportunity having data based upon a difference between the average and a predetermined threshold.