Minimum-Phase Doherty Output Network for Wider RF Bandwidth

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional Doherty amplifiers face challenges with increased PCB area occupation and restricted RF bandwidth due to multiple impedance inverters and offset lines, particularly in N-way configurations, which limits power handling capability and miniaturization efforts.

Innovation Solution

The implementation of an N-way, inverted Doherty amplifier with a minimum phase output network that excludes customary 90-degree impedance inverters and offset lines, utilizing a power splitter and phase shifter array to drive N amplification paths with 90-degree impedance transformers and an offset line, resulting in a more compact design with enhanced RF bandwidth and power handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple impedance inverters and offset lines are used in conventional Doherty amplifiers, then correct phase relationships for optimal load modulation are achieved, but PCB area occupation increases significantly

Engineering Contradiction:
Improvephase relationship accuracyVSAvoidPCB area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the offset lines from the Doherty amplifier architecture. By eliminating these unnecessary transmission line elements, the design achieves correct phase relationships through the inherent phase characteristics of the impedance inverters and power combiner, significantly reducing PCB area occupation while maintaining optimal load modulation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the functions of phase adjustment and impedance transformation into the impedance inverter network itself. The impedance inverters are designed to provide both the required 90-degree phase shift and impedance transformation, eliminating the need for separate offset lines and reducing overall circuit complexity and PCB footprint

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If multiple impedance inverters and offset lines are used in conventional Doherty amplifiers, then optimal load modulation is achieved, but RF bandwidth is restricted

Engineering Contradiction:
Improveload modulation performanceVSAvoidRF bandwidth
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

By removing offset lines from the architecture, the patent eliminates the bandwidth limitations imposed by these transmission line elements. The load modulation performance is maintained through optimized impedance inverter design that provides the necessary phase relationships across a broader frequency range, enabling enhanced RF bandwidth

Inventive Principle:
Principle #2Taking out (Extraction)

3Area of stationary object

If some transmission line elements have relatively high characteristic impedances, then circuit compactness is achieved, but power handling capability is limited

Engineering Contradiction:
Improvecircuit areaVSAvoidpower handling capability
Core Design Contradiction:
Area of stationary objectVSPower

Solution Approach 1:

The patent optimizes the characteristic impedance parameters of the transmission line elements in the output matching networks. By selecting appropriate impedance values that balance compactness and power handling requirements, the design achieves both circuit miniaturization and adequate power handling capability for practical amplifier applications

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3255788B1Doherty amplifiers with minimum phase output networks
Publication Date: 2021.03.10 NXP USA INC
  • EP3255788B1 patent drawingFigure 1
  • EP3255788B1 patent drawingFigure 2
  • EP3255788B1 patent drawingFigure 3

AI summary

A Doherty amplifier (200) includes an output combining network (272) that has a first combining network input coupled to a main amplifier path, a lowest-order combining network input coupled to a lowest-order peaking amplifier path, and N-2 additional combining network inputs coupled to other peaking amplifier paths. A final summing node (273) is coupled to the combining network output (204), and is directly coupled to the first combining network input. N-2 intermediate summing nodes are coupled to the N-2 additional combining network inputs. An offset line (287) is coupled between the lowest-order combining network input and a lowest-order summing node. A longest phase delay imparted by the output combining network (272) on a peaking RF signal between the lowest-order combining network input and the final summing node (273) is greater than all other phase delays imparted on any other RF signal provided to the first combining network input and the N-2 additional combining network inputs.