Minority Carrier Conversion Structure for Parasitic Current Suppression
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Solution Overview
Problem
In integrated semiconductor devices, the lateral flow of minority carriers from power devices to logic devices can cause undesirable potential drops and trigger parasitic devices, disrupting logic device functionality when the power device is reverse biased.
Innovation Solution
A minority carrier conversion structure is implemented in the semiconductor substrate, comprising doped regions of different conductivity types and a conducting layer that intercepts minority carriers and converts them into majority carriers, reducing lateral parasitic bipolar current flow by positioning the doped regions closer to the logic device well than the power device well.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power device is reverse biased to provide reverse current capability, then the useful reverse current flows through the power device, but minority carriers laterally flow into the logic device well causing potential drops and triggering parasitic devices
Solution Approach 1:
A minority carrier conversion structure is introduced as an intermediary element between the power device well and the logic device well. This structure includes a first doped region of the same conductivity type as the wells, a second doped region of opposite conductivity type, and a conducting layer connecting them. The conversion structure intercepts minority carriers before they can laterally flow into the logic device well, converting them to majority carriers and preventing the harmful lateral current flow while allowing the power device to maintain its reverse current capability
Solution Approach 2:
The harmful minority carrier current flow is extracted and redirected away from the logic device well path. The minority carrier conversion structure captures the minority carriers that would otherwise flow laterally into the logic device, removing them from the harmful lateral flow path and converting them into majority carriers that can be safely handled by the substrate and doped regions
2Productivity
If the separation region between power device well and logic device well is reduced to increase device density, then more devices can be integrated, but minority carrier lateral flow increases triggering parasitic devices
Solution Approach 1:
The minority carrier conversion structure serves as a mediator in the separation region between the power device well and logic device well. It actively manages the minority carrier population in this critical transition zone, converting minority carriers to majority carriers before they can trigger parasitic devices, thereby enabling closer spacing of devices without compromising reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively suppresses lateral parasitic bipolar current flow, ensuring proper operation of logic devices by intercepting and converting minority carriers, thereby reducing minority carrier lifetime and preventing parasitic device turn-on, especially at high reverse substrate biases.
Implementation Method 1
A minority carrier conversion structure is implemented in the semiconductor substrate, comprising doped regions of different conductivity types and a conducting layer that intercepts minority carriers and converts them into majority carriers
Implementation Method 2
The minority carrier conversion structure comprises a first doped region of the same conductivity type as the first and second wells that extends into the semiconductor substrate from the first main surface, a second doped region of the opposite conductivity type as the first doped region
Data Source
AI summary
According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.