Memory-in-pixel circuit simplifies LCD manufacturing complexity

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Solution Overview

Problem

The manufacturing process of memory-in-pixel (MIP) circuits is complex and costly due to their composition of CMOS circuits, which hinders the development of low-power consumption LCD display technologies.

Innovation Solution

An MIP circuit design featuring a first and second voltage terminal, input terminals, control terminals, and an output terminal, with specific transistor configurations and control sub-circuits to manage node potentials and enable conduction based on control signals, simplifying the structure and reducing manufacturing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If MIP circuit uses CMOS circuit composition, then memory function and pixel integration are achieved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvememory function integrationVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent changes the fundamental parameter of circuit composition from CMOS to a simplified transistor-based circuit with specific configurations (first transistor with first electrode to first node, second transistor with first electrode to second node, etc.). This parameter change maintains the memory function while reducing manufacturing complexity by avoiding complex CMOS processes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the MIP circuit into distinct functional blocks: input circuit (with first and second input terminals), control circuit (with first and second control terminals), output circuit (with output terminal), and voltage terminals. This segmentation allows each part to be optimized independently and simplifies the overall manufacturing process compared to integrated CMOS implementation.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If MIP circuit uses simplified structure, then manufacturing cost and complexity are reduced, but power consumption control may be affected

Engineering Contradiction:
Improvecircuit structureVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic control of the circuit elements through control terminals that can switch transistors on and off based on input signals. The first transistor and second transistor are dynamically controlled to connect or disconnect their respective first nodes and second nodes, enabling the circuit to adapt its power consumption to the operational requirements while maintaining a simple structure.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit design allows the transistors and nodes to self-regulate their states based on the input and control signals received. The first transistor automatically connects the first node when its control condition is met, and the second transistor similarly controls the second node, eliminating the need for complex external control mechanisms while maintaining low power consumption.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10991333B2Memory-in-pixel circuit and driving method thereof, and liquid crystal display panel including the same
Publication Date: 2021.04.27 BEIJING BOE OPTOELECTRONCIS TECH CO LTD
  • US10991333B2 patent drawing
  • US10991333B2 patent drawing
  • US10991333B2 patent drawing

AI summary

A memory in-pixel (MIP) circuit, a driving method of the MIP circuit, and an LCD panel fabricated using the MIP circuit. The MIP circuit comprising an input circuit, a control circuit and an output circuit. The input circuit brings the first input terminal and the second input terminal into conduction with a first node and a second node respectively in response to the first control signal of the first control terminal being active. The control circuit is configured to set and maintain the potential of a third node or a fourth node active based on the potential of the first node and the second node. The output circuit is configured to bring the output terminal into conduction with the first or second input terminal according to the potential of the third and the fourth node in response to the second control signal of the second control terminal being active.