Memory in Pixel Circuit Simplification
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Solution Overview
Problem
Current Memory in Pixel (MIP) display technology is complex and has low yield due to its reliance on the CMOS LTPS process, leading to high production costs and limited technological compatibility and application range.
Innovation Solution
A simplified MIP design incorporating a data input unit, data latching circuits, drive control circuits, and a drive circuit using a single type of MOS transistors (either NMOS or PMOS) to store data voltage, allowing for the output of high or low power source voltages and enabling black and white display, while utilizing a single MOS LTPS process for manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS LTPS process is used for MIP display technology, then data storage function is achieved, but process complexity increases and yield decreases
Solution Approach 1:
The patent segments the data storage function into two independent latching circuits (first data latching circuit and second data latching circuit), each using a single type of MOS transistor. This segmentation allows each circuit to be simpler while maintaining the overall data storage capability through coordinated operation of both circuits.
Solution Approach 2:
The patent inverts the conventional approach by using a single type of MOS transistor (either all NMOS or all PMOS) instead of the traditional CMOS complementary structure. This inversion simplifies the manufacturing process while achieving the required data storage function through clever circuit design and control signal coordination.
2Reliability
If CMOS LTPS process is used for MIP display technology, then data storage function is achieved, but production cost increases
Solution Approach 1:
The patent applies homogeneity by using a single type of MOS transistor throughout the entire MIP circuit design. This homogeneous approach using only NMOS or only PMOS transistors simplifies the manufacturing process, reduces production costs, and improves yield while maintaining data storage functionality through the coordinated operation of multiple latching circuits.
3Reliability
If CMOS LTPS process is used for MIP display technology, then data storage function is achieved, but technological compatibility and application range are limited
Solution Approach 1:
The patent achieves universality by designing a MIP circuit that can be implemented using a single type of MOS transistor, making it compatible with various manufacturing processes beyond the specific CMOS LTPS process. This universal design approach enhances technological compatibility and expands application range while maintaining the core data storage function through the latching circuit architecture.
Data Source
AI summary
A memory in pixel, a data storage method, and a pixel array. The memory in pixel includes a data input unit, configured to read data voltage on a data line onto a first data latching terminal and a second data latching terminal; a first data latching circuit, configured to hold a level of the first data latching terminal; a second data latching circuit, configured to hold a level of the second data latching terminal; a drive control circuit, configured to enable a level of a drive node to be opposite to that of the first data latching terminal; and a drive circuit, configured to output a third power source voltage of a third power source voltage terminal to a output terminal and output a fourth power source voltage of a fourth power source voltage terminal to the output terminal.