MIPI C-PHY Receiver Circuit for CMOS Image Sensor Testing
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Solution Overview
Problem
The existing test processes for CMOS image sensors using the C-PHY interface face challenges in replicating field operations due to significant distance differences between the sensor and test devices, leading to signal loss and increased manufacturing costs.
Innovation Solution
A receiving circuit with amplifying, filtering, and branching capabilities is integrated into a printed circuit board, reducing signal loss and allowing efficient test output signal reception, while being cost-effective by avoiding the need for application-specific integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the distance between CMOS image sensor and test device is increased to replicate field operations, then the test process more closely resembles field operations, but signal loss increases
Solution Approach 1:
An equalization circuit is introduced as an intermediary component between the CMOS image sensor and test device. This circuit compensates for signal degradation caused by long transmission distances, enabling accurate testing while maintaining signal integrity over extended distances comparable to actual mobile device operations.
Solution Approach 2:
The equalization circuit dynamically adjusts signal parameters (voltage levels, timing characteristics) to compensate for transmission distance effects. By changing these parameters in real-time based on transmission conditions, the system maintains signal quality even when distance is increased to replicate field operations.
2Reliability
If an application-specific integrated circuit (ASIC) is used for the receiving circuit, then signal reception performance is improved, but manufacturing cost increases
Solution Approach 1:
The receiving circuit is designed with universal components that can serve multiple functions. Rather than using a dedicated ASIC for each specific test function, the same receiving circuit infrastructure handles various test operations, reducing overall manufacturing costs while maintaining reliable signal reception performance.
Solution Approach 2:
Instead of manufacturing expensive custom ASICs for each test scenario, the patent uses standardized circuit designs that can be replicated and reused across different test configurations. This approach maintains consistent performance while significantly reducing per-unit manufacturing costs through economies of scale.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces signal loss and lowers manufacturing costs by efficiently receiving test output signals from CMOS image sensors through the MIPI C-PHY interface, closely replicating field operations and enabling efficient testing.
Implementation Method 1
an amplifying circuit, a filtering circuit and a branch circuit. The amplifying circuit receives a plurality of multi-level signals and amplifies the plurality of multi-level signals to generate a plurality of amplified signals
Implementation Method 2
The filtering circuit filters the plurality of amplified signals to generate a plurality of filtering signals
Data Source
AI summary
A receiver, which is compatible with a mobile industry processor interface (MIPI) C-PHY physical layer, includes a plurality of variable-gain amplifiers responsive to respective multi-level signals (e.g., 3-level signals), and a plurality of filters having variable cutoff frequencies. The plurality of filters are responsive to respective signals generated by the plurality of amplifiers. An array of comparators is provided, which is responsive to signals generated by the plurality of filters. A jitter detection circuit is provided, which is configured to set respective gains of the plurality of variable-gain amplifiers and respective cutoff frequencies of the plurality of filters (e.g., high-pass filters), in response to signals generated by the array of comparators.