MIPI D-PHY Link Rate Enhancement via Data Lane Clock Extraction
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Solution Overview
Problem
Current high-speed data communications interfaces face limitations in maximum data rates due to signal transition times and clock signal transmission, necessitating improved clock generation and data sampling techniques for multi-lane differential data communication links.
Innovation Solution
The method involves detecting transitions in data and clock signals to generate a receiver clock signal, which is used to capture data, with techniques such as double data rate clock alignment and strobe signal usage to manage transitions and deserialize data, effectively ignoring additional transitions after the edge is generated to maintain reliable data capture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequencies are increased to improve data transfer rates, then productivity increases, but signal transition times and transmission limitations cause reliability to deteriorate
Solution Approach 1:
The patent extracts clock information from the data lanes themselves rather than relying on separate clock signal transmission. By detecting transitions in the data signals and using them to generate the receiver clock signal, the system eliminates the need for dedicated clock lane transmission, thereby improving reliability while maintaining high data transfer rates.
Solution Approach 2:
The data lanes serve dual purposes: transmitting data and providing clock timing information. The transitions in the data signals are self-utilized to generate the receiver clock signal, making the system self-sufficient and eliminating the need for external clock signal transmission that would limit reliability at high frequencies.
2Ease of operation
If separate clock signal transmission is used, then clock management is simplified, but device complexity increases due to additional clock lanes required
Solution Approach 1:
The patent merges the clock function with the data transmission function by using the same data lanes to carry both data and timing information. This consolidation eliminates the need for separate clock lanes, reducing device complexity while maintaining effective clock management through transition-based clock signal generation.
Solution Approach 2:
The data lanes are designed to serve multiple functions: data transmission and clock signal generation. By making the data lanes universal, the system eliminates dedicated clock lanes, thereby reducing overall device complexity while maintaining clock management capabilities through the extracted transition signals.
3Reliability
If transition detection is used to generate clock edges, then data capture reliability improves, but additional transitions after edge generation cause measurement precision to deteriorate
Solution Approach 1:
The patent applies preliminary filtering to the detected transitions before generating clock edges. By identifying and selecting only the relevant first transition and ignoring subsequent transitions within the same data period, the system ensures precise clock edge timing while maintaining reliable data capture.
Solution Approach 2:
The system uses feedback mechanisms to monitor detected transitions and determine whether additional transitions have occurred after an edge is generated. This feedback allows the system to selectively ignore spurious transitions, thereby maintaining measurement precision while preserving data capture reliability.
Data Source
AI summary
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.