MIPI D-PHY Receiver With Switch-Based Test Loopback

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Solution Overview

Problem

Traditional MIPI D-PHY Universal Lane configurations face limitations in data rate due to high parasitic capacitance and overhead, which is not suitable for safety-sensitive applications requiring full-speed in-system testability and diagnostics.

Innovation Solution

A MIPI D-PHY receiver configuration with reduced transmitter count, utilizing switches to disconnect test signals and tri-state transmitters, allowing for efficient data transmission and fault detection, combining the benefits of RX and Universal Lane configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If D-PHY Universal Lane configuration is used to support testability, then test capability is improved, but parasitic capacitance increases and data rate is limited

Engineering Contradiction:
Improvetest capabilityVSAvoiddata rate
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the transmitter functionality by using only one transmitter per lane for both TX and test operations, rather than having separate transmitters for TX and RX functions. This segmentation reduces the number of active transmitters and associated parasitic capacitance, enabling higher data rates while maintaining test capability through the loopback mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies universality by making a single transmitter serve multiple functions: it acts as the TX transmitter during normal operation and as the test signal source during test mode. The receiver similarly serves dual purposes as both RX receiver and loopback test receiver. This multi-functionality eliminates the need for dedicated test transmitters, reducing overhead and parasitic capacitance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If both HS and LP TX are included in each data lane for RX application, then receive capability is improved, but area and power overhead increase

Engineering Contradiction:
Improvereceive capabilityVSAvoidtransmitter area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the unnecessary LP transmitter from the RX-only configuration. Since low-power mode transmission is not required for receive-only applications, eliminating the LP TX block reduces area and power consumption while maintaining full receive capability through the high-speed transmitter.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operational parameters by configuring the single high-speed transmitter to handle both high-speed transmission and low-power mode transmission needs. The transmitter can dynamically switch between HS and LP modes based on requirements, eliminating the need for separate dedicated transmitters for each mode and reducing overall area.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If both HS and LP TX are included in each data lane for RX application, then receive capability is improved, but power consumption increases

Engineering Contradiction:
Improvereceive capabilityVSAvoidstandby power
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent extracts and removes the LP transmitter block from RX-only configurations, eliminating its associated standby power consumption. The high-speed transmitter is configured to handle both HS and LP mode operations, reducing the total number of active power-consuming blocks while maintaining full receive functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The high-speed transmitter is designed with universal capability to operate in both high-speed and low-power modes. This multi-functionality allows a single transmitter to replace what would traditionally require two separate transmitters, significantly reducing standby power consumption while maintaining full receive capability across different operational modes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If multiple transmitters are used for Universal Lane configuration, then testability is improved, but area and power overhead increase

Engineering Contradiction:
ImprovetestabilityVSAvoidtransmitter area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies universality by configuring a single transmitter to serve dual purposes: acting as the normal TX transmitter during data transmission and as the test signal generator during test operations. The receiver similarly serves as both RX receiver and loopback test receiver. This eliminates the need for dedicated test transmitters, reducing area overhead while maintaining full testability through the loopback mechanism.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the TX and test signal generation functions into a single transmitter block. Instead of having separate transmitters for normal operation and testing, the same transmitter is used for both purposes by switching its operation mode. This merging reduces the total transmitter count and associated area while preserving test capability through the receiver loopback path.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10664371B2Differential physical layer device with testing capability
Publication Date: 2020.05.26 MIXEL INC
  • US10664371B2 patent drawing
  • US10664371B2 patent drawing
  • US10664371B2 patent drawing

AI summary

A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.