MIPI I3C Bus Image Transfer for Low Power SoCs
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Solution Overview
Problem
Current high power/high bandwidth interfaces like MIPI CSI-2 and USB are challenging for low power scenarios and require high enablement costs and complexities due to high speed SerDes blocks, making them unsuitable for low power applications such as wake on face implementations.
Innovation Solution
Implementing image data transfers over MIPI Inter-Integrated Circuit (I2C) and/or improved Inter-Integrated Circuit (I3C) buses, which are less complex and require lower power, by mapping CSI-2 frame formats onto I3C packets and providing scalable architectures on both SoC and camera sides, with error checks and retries for reliability, and using I3C for low power scenarios and CSI-2/USB for high performance applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high power/high bandwidth interfaces (MIPI CSI-2, USB) are used for camera image transfer, then image transfer bandwidth and speed are improved, but power consumption increases and device complexity increases due to high speed SerDes blocks
Solution Approach 1:
The patent implements dynamic interface selection where the system can switch between I3C and CSI-2 interfaces based on operational requirements. The camera controller dynamically configures the interface type and data rate according to whether low-power operation or high-speed streaming is needed, allowing the system to adapt its performance characteristics to match actual usage scenarios.
Solution Approach 2:
The patent changes the operational parameters by using I3C interface with lower data rates (e.g., 25 Mbps per lane) compared to traditional CSI-2 high-speed interfaces. The system adjusts the data transfer rate parameter to match the lower power consumption requirements of I3C while maintaining sufficient bandwidth for low-power applications like wake-on-face functionality.
2Productivity
If high power/high bandwidth interfaces (MIPI CSI-2, USB) are used for camera image transfer, then image transfer bandwidth is improved, but device complexity and enablement costs increase due to high speed SerDes blocks
Solution Approach 1:
The patent employs I3C interface as a simpler, lower-cost alternative to expensive high-speed SerDes blocks required for CSI-2 and USB interfaces. The I3C interface uses standard I2C infrastructure with lower enablement costs and reduced complexity, making it suitable for applications where maximum bandwidth is not critical but cost and complexity reduction are priorities.
Solution Approach 2:
The patent makes the camera interface system universal by supporting multiple interface types (I3C and CSI-2) through a single camera controller that can dynamically switch between them. This multi-functionality allows the same camera hardware to serve both low-power applications (using I3C) and high-performance applications (using CSI-2), eliminating the need for separate hardware implementations for different use cases.
3Use of energy by moving object
If I3C interface is used for low power scenarios, then power consumption is reduced, but data transfer bandwidth is limited compared to CSI-2/USB interfaces
Solution Approach 1:
The patent segments the image transfer functionality into different modes: low-power mode using I3C interface for applications like wake-on-face where only small amounts of data need to be transferred, and high-performance mode using CSI-2 interface for video streaming and other bandwidth-intensive applications. This segmentation allows the system to optimize for power consumption when bandwidth requirements are low, while maintaining high bandwidth capability when needed.
Solution Approach 2:
The system dynamically adapts the interface type and data transfer rate based on the specific application requirements. For low-power scenarios, the system selects I3C interface with appropriate data rates to minimize power consumption while maintaining sufficient bandwidth for the task. For high-performance scenarios, the system switches to CSI-2 interface to provide maximum bandwidth, thus dynamically balancing power consumption and bandwidth requirements.
Data Source
AI summary
In one embodiment, a system includes a host system-on-chip (SoC) comprising vision processing circuitry and a camera connected to the host SoC through an Inter-Integrated Circuit (I3C) bus. The camera includes circuitry to generate image data and transmit an interrupt signal to the host SoC over the I3C bus indicating the image data is ready for transfer. The host SoC vision processing circuitry is to transmit a read message to the camera over the I3C bus based on the interrupt signal and receive a set of line payload packets including the image data over the I3C bus based on the read message.