MIPI M-PHY Port Synchronization for Hibern8 Entry

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Solution Overview

Problem

The challenge in MIPI M-PHY technology is synchronizing the entry into the HIBERN8 low-power state across ports, which requires precise timing and clock synchronization to ensure that the receiver enters HIBERN8 before the transmitter, but this is rarely achievable due to differing clock frequencies and lack of common configuration clocks.

Innovation Solution

The method involves sending an electrical idle ordered set (EIOS) from the transmitter to the receiver to synchronize the transition from high-speed burst to STALL state, followed by a reconfiguration trigger to initiate the HIBERN8 state, ensuring the receiver enters HIBERN8 before the transmitter, and maintaining this order across all lanes to ensure proper synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the receiver and transmitter use different clock frequencies, then the system has greater flexibility in operation, but precise timing synchronization for entering HIBERN8 state cannot be achieved

Engineering Contradiction:

Improveoperational flexibilityVSAvoidtiming synchronization precision

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary synchronization mechanism using EIOS (Electrical Idle Ordered Set) signals and reconfiguration triggers as中介 to coordinate the timing between transmitter and receiver. These intermediary signals mediate the transition process, allowing the receiver to enter HIBERN8 before the transmitter even when using different clock frequencies, thus resolving the timing precision issue while maintaining operational flexibility

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the receiver enters HIBERN8 before the transmitter, then proper synchronization and data integrity are ensured, but the timing control becomes more complex

Engineering Contradiction:

Improvedata integrityVSAvoidtiming control complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by having the receiver enter the HIBERN8 state before the transmitter through a predetermined sequence of events. The receiver receives the EIOS signal, processes it, and enters HIBERN8 in advance of the transmitter, which is triggered by a reconfiguration trigger signal. This preliminary timing arrangement ensures data integrity while the complexity is managed through standardized protocol sequences

Inventive Principle:

Principle #10Preliminary action

3Productivity

If HIBERN8 state is entered quickly, then productivity is improved, but power consumption during transition increases

Engineering Contradiction:

Improvewakeup speedVSAvoidtransition power consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic action through the use of structured transition sequences involving EIOS signals and reconfiguration triggers. The system uses periodic signaling patterns to manage the transition into and out of HIBERN8 state, allowing for optimized power management during transitions while maintaining the ability for quick wakeups when needed. The periodic nature of these control signals enables efficient energy usage during state transitions

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS9753529B2Systems, apparatuses, and methods for synchronizing port entry into a low power status

Publication Date: 2017.09.05 INTEL CORP

AI summary

Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.