MIPI-PHY Receiver Voltage-Based Masking Control
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Solution Overview
Problem
Current MIPI D-PHY receivers require significant software resources to determine the masking period for high-speed data reception and struggle with handling signal frequencies that do not comply with specifications, leading to inefficiencies and errors.
Innovation Solution
An MIPI D-PHY receiver that determines the start and end of the masking period based on the voltage characteristics of differential signals DP and DN, eliminating the need for software detection and enabling handling of non-compliant signal frequencies through a control module, data receiving circuit, masking circuit, and bias circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based detection and hand-shaking is used to determine UI length and masking period, then the receiver can identify clock signal parameters, but software resources are significantly consumed and non-compliant signal frequencies cannot be handled
Solution Approach 1:
The patent replaces the software-based detection mechanism with a hardware-based voltage detection mechanism. The control module directly monitors the voltage levels of differential signals DP and DN to determine masking period boundaries, eliminating the need for software hand-shaking and UI length detection. This substitution resolves the contradiction by removing software resource consumption while maintaining reliable detection of signal parameters including non-compliant frequencies.
Solution Approach 2:
The receiver performs self-determination of the masking period by autonomously detecting voltage characteristics of the differential signals. Instead of relying on external software communication with the transmitter, the control module independently identifies the start and end of the masking period through voltage threshold detection, enabling the system to handle various signal frequencies without software intervention.
2Productivity
If the receiver enters high-speed mode in period T2 as required by MIPI specifications, then the receiver can prepare for high-speed data reception, but the signals DP and DN having the same voltage potential in period T2 are invalid and unrecognizable
Solution Approach 1:
The receiver enters high-speed mode in period T2 and performs preliminary preparation for data reception, while the control module simultaneously applies a bias voltage to maintain the output signal in a known first state. This preliminary action allows the receiver circuitry to be ready for high-speed operation while the bias voltage compensates for the unrecognizable signals during this transition period.
Solution Approach 2:
The control module applies a bias voltage in period T2 to counteract the effect of invalid signals DP and DN that have the same voltage potential. This preliminary anti-action prevents the unrecognizable signals from causing erroneous data reception by forcing the output signal into a controlled first state before valid high-speed data transmission begins in period T3.
3Reliability
If a masking period is applied to ignore data in period T2 and part of T3, then the receiver avoids processing invalid signals, but the masking period length must be precisely determined which requires learning UI value
Solution Approach 1:
The patent changes the parameter used for determining masking period boundaries from time-based (requiring UI length knowledge) to voltage-based. The control module monitors voltage levels of the differential signals and detects transitions between voltage states to automatically determine the start and end of the masking period, eliminating the need to learn or know the UI clock period value.
Solution Approach 2:
The control module acts as an intermediary that translates the voltage characteristics of differential signals DP and DN into control signals for the masking circuit. By using voltage level transitions as an intermediate indicator, the system can determine masking period boundaries without directly measuring or knowing the clock signal period UI, simplifying the determination process.
Data Source
AI summary
A receiver includes a control module, a data receiving circuit and a masking circuit. The control circuit generates an enable signal according to a pair of differential signals provided by a transmitter. Triggered by the enable signal, the data receiving circuits generates an output signal according to the differential signals, and the masking circuit starts masking the output signal. After generating the enable signal, the control module starts providing a bias voltage to the differential signals such that the output signal has a first state. The transmitter adjusts the differential signals to render the output signal to enter a second state from the first state. Upon detecting the output signal having entered the second state, the control module stops providing the bias voltage and generates a disable signal to prompt the masking circuit to stop masking the output signal.