Shared MIPI C-PHY/D-PHY Receiver Circuit for Smaller Interface ICs
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Solution Overview
Problem
There is a need for semiconductor devices that can support both MIPI D-PHY and MIPI C-PHY specifications while minimizing circuit size, as integrating multiple independent communication interfaces increases circuit size unnecessarily.
Innovation Solution
A semiconductor device configuration that includes external connection terminals, receivers, a C-PHY block, a D-PHY block, and a main processing section, which can selectively process signals according to either MIPI C-PHY or MIPI D-PHY specifications, allowing for reduced circuit size by sharing components and switching between communication schemes within the driver IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple independent communication interfaces (MIPI D-PHY and MIPI C-PHY) are monolithically integrated in a semiconductor device, then both communication specifications are supported, but the circuit size increases
Solution Approach 1:
The patent implements a unified receiver structure that can operate in both MIPI D-PHY and MIPI C-PHY modes. The receiver includes differential input terminals that can receive either differential signals (D-PHY) or single-ended signals (C-PHY), and a processing section that adaptively processes signals based on the selected mode. This multi-functional design allows one receiver to replace what would traditionally require two separate receivers, thereby supporting both specifications while reducing circuit size.
Solution Approach 2:
The patent merges the D-PHY and C-PHY interface functions into a single integrated block. The receiver structure combines differential signal processing capability (for D-PHY) and single-ended signal processing capability (for C-PHY) within the same hardware. The processing section integrates both D-PHY processing logic and C-PHY processing logic, allowing the system to switch between modes without requiring separate independent interfaces, thus reducing overall circuit area.
2Adaptability or versatility
If separate independent communication interfaces are provided for MIPI D-PHY and MIPI C-PHY, then both specifications can be supported independently, but the device complexity increases
Solution Approach 1:
The receiver is designed as a universal interface that can handle both MIPI D-PHY and MIPI C-PHY protocols. The differential input terminals can accept differential signals when operating in D-PHY mode and single-ended signals when operating in C-PHY mode. The processing section contains adaptive logic that processes signals differently based on the selected mode, eliminating the need for separate independent interfaces for each specification.
Solution Approach 2:
The patent implements dynamic switching capability within the receiver. A mode selection mechanism allows the system to switch between D-PHY and C-PHY operating modes based on external control signals. The processing section dynamically adjusts its behavior: in D-PHY mode it processes differential signals with clock lane and data lane separation, while in C-PHY mode it processes single-ended signals with embedded clock functionality. This dynamic adaptability reduces device complexity by using one configurable interface instead of multiple fixed interfaces.
Data Source
AI summary
A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.