MIPI RFFE Bus Combining for Clock-Free Multiband RF Control
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Solution Overview
Problem
Existing MIPI RFFE serial bus architectures cannot accommodate multiple buses due to non-deterministic clocks, preventing simultaneous control of RF Front-End circuits for different frequency bands like 4G and 5G technologies.
Innovation Solution
Implementing a circuit with decoders, multiplexers, and selection circuits that utilize write-complete signals to ensure synchronization in a clock-free manner, allowing common control of agent devices by multiple MIPI RFFE serial buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single MIPI RFFE serial bus is used to control RF Front-End circuits, then clock synchronization is maintained, but the system cannot accommodate multiple buses for different frequency bands (4G and 5G)
Solution Approach 1:
The patent combines multiple MIPI RFFE serial buses (first bus and second bus) into a unified control architecture that shares common decoders and control resources. This merging approach enables the system to support multiple frequency bands (4G and 5G) while avoiding the complexity of completely separate bus implementations, as the buses share common infrastructure components like decoders and control logic.
Solution Approach 2:
The patent implements universal decoders that can handle commands from multiple different MIPI RFFE serial buses simultaneously. These decoders are designed to be multi-functional, accepting and processing control commands for different frequency bands through a single interface, thereby enabling one bus architecture to serve multiple purposes and support both 4G and 5G technologies.
2Adaptability or versatility
If multiple MIPI RFFE serial buses are implemented simultaneously, then control of multiple frequency bands is enabled, but non-deterministic clocks prevent synchronization
Solution Approach 1:
The patent extracts the clock synchronization problem from the bus architecture by removing the requirement for deterministic clocks in multiple buses. Instead of relying on synchronized clocks across multiple buses, the invention separates the control commands from the timing-critical functions, allowing buses to operate with independent, non-deterministic clocks while maintaining reliable control through asynchronous command processing.
Solution Approach 2:
The patent introduces decoders as intermediary components that mediate between multiple MIPI RFFE serial buses and the RF Front-End circuits. These decoders act as buffers and translators, receiving commands from multiple buses with non-deterministic clocks and processing them in a synchronized manner, thereby decoupling the clock synchronization requirement from the bus architecture itself.
3Adaptability or versatility
If separate control buses are used for 4G and 5G RF Front-End circuits, then frequency band independence is achieved, but system complexity and implementation difficulty increase
Solution Approach 1:
The patent merges the control paths for 4G and 5G RF Front-End circuits into a shared bus architecture. Instead of implementing completely separate physical buses for each frequency band, the invention combines them into a unified system that uses common infrastructure components, thereby maintaining frequency band independence while significantly reducing implementation complexity and manufacturing difficulty.
Solution Approach 2:
The patent segments the control function into independent decoder units that can be selectively activated for different frequency bands. This segmentation allows the system to maintain independence for 4G and 5G control while sharing common infrastructure, as each band's control requirements are handled by dedicated decoder segments rather than requiring entirely separate bus implementations.
Data Source
AI summary
Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.