MIPI Transceiver Clock Embedding Without a Dedicated Clock Line
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Solution Overview
Problem
In display devices using the MIPI protocol, the presence of a separate clock line increases physical and spatial costs as well as power consumption during internal communication.
Innovation Solution
The transceiver configuration omits the clock line by embedding clock information within the data channels, using encoders and decoders to encode and decode data that includes clock information, allowing effective communication without a dedicated clock line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate clock line is used for MIPI protocol communication, then reliable clock synchronization is achieved, but physical cost and power consumption increase
Solution Approach 1:
The patent combines the clock signal and data signals into a single communication channel. The transmitter modulates the clock information onto the data lines by controlling the timing and transition patterns of data bits, eliminating the need for a separate clock line while maintaining synchronization reliability.
Solution Approach 2:
The data lines are designed to serve dual functions: transmitting both data information and clock synchronization information. By encoding clock signals through data transitions and using specific bit patterns (such as alternating 1010 patterns for clock establishment), the same physical medium performs multiple communication tasks.
2Reliability
If a separate clock line is used for MIPI protocol communication, then clock synchronization is maintained, but physical space and device complexity increase
Solution Approach 1:
The patent merges the clock line function into the existing data lines, reducing the total number of physical connections required. This integration simplifies the overall device structure and reduces spatial requirements while maintaining the essential clock synchronization capability through intelligent signal encoding.
Solution Approach 2:
The patent extracts the clock synchronization function from a separate dedicated line and implements it within the data transmission protocol itself. By removing the redundant clock line and embedding clock information in the data signal transitions, the system achieves simpler physical architecture without sacrificing synchronization reliability.
3Speed
If data is transmitted without encoding, then transmission speed is high, but data integrity deteriorates due to consecutive identical bits
Solution Approach 1:
The patent applies encoding schemes that change the parameter of bit transitions to ensure data integrity. By preventing consecutive identical bits through encoding (such as adding transition bits or using differential encoding), the system maintains reliable clock recovery and data detection without significantly compromising transmission speed.
Solution Approach 2:
The patent performs preliminary encoding of data before transmission to prevent problematic patterns. By pre-processing the data stream to eliminate consecutive identical bits and establish proper transition patterns, the system ensures both data integrity and reliable clock synchronization from the start of transmission.
Data Source
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AI summary
A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.