MIPI Transceiver Clock Recovery Without a Separate Clock Line
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Solution Overview
Problem
Display devices using the MIPI protocol face increased physical costs and power consumption due to the need for a separate clock line, which also prolongs the locking time for clock training patterns.
Innovation Solution
A transceiver system that includes a transmitter and receiver connected through multiple lines, where the transmitter sequentially transmits signals with different voltage ranges and clock training patterns, allowing the receiver to generate clock signals using clock data recovery circuits and registers that store frequency and phase information, thereby reducing the time required to track and lock onto these patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate clock line is used in MIPI protocol, then clock signal transmission is improved, but physical cost and power consumption increase
Solution Approach 1:
The patent merges the clock signal transmission function into the existing data transmission lines by encoding clock information within the data signals. The transmitter embeds clock training patterns within the data payload, allowing the receiver to extract clock signals through clock data recovery circuits without requiring separate dedicated clock lines, thus reducing physical cost and power consumption while maintaining reliable clock signal transmission
Solution Approach 2:
The data transmission lines are given multi-functionality by enabling them to carry both data information and clock synchronization information. The clock training patterns are transmitted within the same physical medium as data, making the data lines universal carriers for both types of information, eliminating the need for separate clock lines
2Reliability
If a separate clock line is used in MIPI protocol, then clock signal transmission is improved, but physical cost increases
Solution Approach 1:
The patent merges the clock signal transmission function into the existing data transmission lines by encoding clock information within the data signals. The transmitter embeds clock training patterns within the data payload, allowing the receiver to extract clock signals through clock data recovery circuits without requiring separate dedicated clock lines, thus reducing physical cost and power consumption while maintaining reliable clock signal transmission
Solution Approach 2:
The patent extracts the clock signal from what would traditionally require a separate physical line and instead derives it from the data transmission medium. The clock data recovery circuit extracts clock training patterns from the received data signals, removing the need for separate clock line infrastructure
3Reliability
If traditional clock training pattern transmission is used, then clock synchronization is achieved, but locking time is prolonged
Solution Approach 1:
The patent applies preliminary action by pre-processing the received signal through equalization before clock recovery. The equalizer compensates for channel distortions in advance, preparing the signal for faster and more accurate clock training pattern detection, thereby reducing the time required to achieve clock synchronization
Solution Approach 2:
The patent implements feedback mechanisms in the clock data recovery circuit that continuously monitor and adjust the recovered clock signal. This feedback enables faster convergence during clock training by correcting deviations in real-time, significantly reducing the locking time while maintaining accurate clock synchronization
Data Source
AI summary
A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1−1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1−1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.