MIPI Transceiver Clock Line Removal via Mode Signaling
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Solution Overview
Problem
In display devices that use the MIPI protocol for internal communication, the presence of a clock line increases physical and spatial costs as well as power consumption.
Innovation Solution
A transceiver system that communicates using the MIPI protocol without a clock line, utilizing a transmitter and receiver connected through two lines, which switch between single-ended and differential signaling modes to transmit signals with different voltage ranges, including a clock training pattern to generate a clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock line is used for MIPI communication, then communication reliability is improved, but physical cost and power consumption increase
Solution Approach 1:
The patent extracts the clock function from a separate dedicated clock line and integrates it into the data lines through mode signaling. The receiver identifies transmission modes (single-ended or differential) based on voltage level patterns in the data lines, thereby removing the need for separate clock lines while maintaining reliable communication.
Solution Approach 2:
The data lines are designed to serve multiple functions: they transmit both data and clock information. By using mode signaling embedded in the voltage levels of these same lines, the system achieves multi-functionality where the first and second lines handle both data transmission and clock synchronization without requiring additional dedicated clock lines.
2Reliability
If a clock line is used for MIPI communication, then communication reliability is improved, but power consumption increases
Solution Approach 1:
The clock function is extracted from a separate physical line and integrated into the existing data transmission lines through mode signaling. This eliminates the need for additional clock line power consumption while maintaining the timing and synchronization functions necessary for reliable communication.
Solution Approach 2:
The same transmission lines are used for both data and clock functions. By encoding mode information in voltage levels on these universal lines, the system reduces overall power consumption by eliminating redundant dedicated clock line power requirements while maintaining communication reliability.
3Device complexity
If single-ended signaling is used, then device complexity is reduced, but noise immunity deteriorates
Solution Approach 1:
The system dynamically switches between single-ended and differential signaling modes based on transmission requirements. The receiver detects the operating mode through voltage level patterns in the data lines and adjusts its processing accordingly, allowing the system to use simpler single-ended mode when possible and more robust differential mode when noise immunity is required.
Solution Approach 2:
The signaling parameters are changed dynamically between single-ended and differential modes. By modifying the voltage level relationships and signaling characteristics based on transmission conditions, the system can optimize between complexity and noise immunity by selecting the appropriate parameter set for each transmission scenario.
Data Source
AI summary
A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. When transmitting a first payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and the transmitter transmits a clock training pattern and the first payload in the second mode.