Mirror Current Read Voltage Reduction for Memory Cell Snapback Prevention
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Solution Overview
Problem
During read operations in memory arrays, unintended voltage levels can snap reset cells, changing their state from reset to set, due to high applied read voltages exceeding the minimum threshold voltage of reset cells, leading to incorrect logic state readings.
Innovation Solution
Implementing a mirror current generation circuitry that reduces the read voltage across memory cells by generating a mirror current at the wordline or bitline node opposite to the sensing circuitry, allowing for immediate sensing without delay, and using a second mirror current to maintain intended current delivery, thus preventing unintended snapbacks of reset cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high read voltage is applied to ensure reliable reading of set cells, then the read reliability is improved, but reset cells may snap unintentionally and change state
Solution Approach 1:
The patent dynamically adjusts the read voltage level based on the sensed state of memory cells. By monitoring cell responses and adapting the voltage magnitude in real-time, the system ensures sufficient voltage for reliable set cell reading while preventing excessive voltage that would cause unintended snapback of reset cells.
Solution Approach 2:
The patent implements a feedback mechanism where the reading circuit senses the state of memory cells during read operations and uses this information to regulate subsequent voltage application. This closed-loop control allows the system to distinguish between set and reset cell responses and adjust voltage levels accordingly, preventing harmful snapback effects.
2Object-affected harmful factors
If voltage regulation is implemented to prevent snapback, then the harmful effects on reset cells are reduced, but the read sense margin deteriorates
Solution Approach 1:
The patent employs dynamic voltage regulation where the read voltage is not fixed but adapts during the read operation based on real-time sensing feedback. This dynamic adjustment allows the system to maintain optimal voltage levels that prevent snapback while preserving sufficient voltage differential for accurate sense margin detection.
Solution Approach 2:
The patent performs preliminary sensing operations before full read voltage application to identify cells that may be susceptible to snapback. By detecting cell states in advance and preparing appropriate voltage levels, the system prevents harmful effects while maintaining read sense margin for cells that require higher voltage for reliable detection.
3Stability of the object's composition
If voltage reduction is applied to prevent snapback, then reset cell stability is improved, but sensing delay increases due to voltage stabilization requirements
Solution Approach 1:
The patent maintains continuous sensing activity during voltage transitions by using feedback mechanisms that allow incremental voltage application and real-time cell state detection. This continuous action eliminates idle stabilization periods, as sensing proceeds throughout the voltage adjustment process without interruption or delay.
Solution Approach 2:
The patent performs preliminary cell state detection at lower voltage levels before applying full read voltage. This preliminary action identifies cells that will snapback, allowing the system to prepare appropriate responses in advance and avoid delays that would result from waiting for voltage stabilization after unintended snapback occurs.
Data Source
AI summary
A method, apparatus and system. The method includes: generating, during a read operation of a memory cell, a mirror current iMir1 at one of a WL node or a BL node of the memory cell opposite, respectively, one of a BL side or a WL side of the memory cell to which a current mode sense circuitry is connected, the iMir1 to reduce a value of the read voltage from VDM1 to VDM2, wherein the read voltage is between the WL node and the BL node; and sensing, using the current mode sense circuitry, a logic state of the memory cell at VDM2.