Mirror Execution Modules for Parallel Memory Access Bottlenecks

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Solution Overview

Problem

In multi-threaded environments, the sharing of a single memory pool among threads leads to memory access bottlenecks, resulting in underutilization of CPU resources and limited computing speed, especially when multiple CPUs are used and memory access times exceed CPU processing times.

Innovation Solution

Creating mirror execution modules with private memory pools for each thread, allowing each thread to access its own memory pool, thereby eliminating the need for thread queuing and optimizing memory access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple threads share a single memory pool to access, then memory resource utilization is improved, but thread waiting time increases and CPU utilization decreases

Engineering Contradiction:
Improvememory resource utilizationVSAvoidthread waiting time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent segments the single shared memory pool into multiple private memory pools, with each thread allocated its own dedicated memory pool. This segmentation eliminates the need for threads to wait for each other when accessing memory, as each thread has exclusive access to its own memory pool. The memory management unit creates and manages these separate memory pools, allowing parallel memory access operations without contention.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If multiple threads share a single memory pool to access, then memory resource utilization is improved, but CPU utilization decreases

Engineering Contradiction:
Improvememory resource utilizationVSAvoidCPU utilization
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the single shared memory pool into multiple private memory pools, with each thread allocated its own dedicated memory pool. This segmentation eliminates the need for threads to wait for each other when accessing memory, as each thread has exclusive access to its own memory pool. The memory management unit creates and manages these separate memory pools, allowing parallel memory access operations without contention.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a single memory pool is shared among threads, then device complexity is reduced, but memory access speed decreases

Engineering Contradiction:
Improvememory management complexityVSAvoidmemory access speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent segments the single shared memory pool into multiple private memory pools, with each thread allocated its own dedicated memory pool. This segmentation eliminates the need for threads to wait for each other when accessing memory, as each thread has exclusive access to its own memory pool. The memory management unit creates and manages these separate memory pools, allowing parallel memory access operations without contention.

Inventive Principle:
Principle #1Segmentation

4Speed

If mirror execution modules are created for each thread, then memory access efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvememory access efficiencyVSAvoidexecution module complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent creates mirror copies of the execution module for each thread, with each copy having access to its own private memory pool. This copying approach allows each thread to execute the same logic independently without interfering with other threads' memory access operations. The memory management unit handles the creation and coordination of these mirror modules, enabling parallel execution with dedicated memory resources.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9448857B2Memory access method for parallel computing
Publication Date: 2016.09.20 FOXIT SOFTWARE TECHNOLOGY HOLDINGS LTD
  • US9448857B2 patent drawing
  • US9448857B2 patent drawing
  • US9448857B2 patent drawing

AI summary

A memory access method is disclosed for computing n parallel threads that invoke one original execution module. The method includes determining a number k (n−1≧k≧1) of k mirror execution modules to be created based on the number of n parallel threads. The method includes determining a mapping policy F between n threads and k+1 execution modules. The k+1 execution modules refer to the original execution module and the k mirror execution modules. The method includes creating the k mirror execution modules and allocating individual private memory to each of the k mirror execution modules. The method includes executing the n parallel threads and making each thread invoke the execution module according to the mapping policy F, with each execution module only accessing its private memory pool. The method includes, after the n parallel threads are finishing executing, deleting the k mirror execution modules and releasing the resources.