Mirror-Type Full Adder Circuit Layout for Reduced Delay
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Solution Overview
Problem
Full adder circuits in logic devices face challenges in reducing calculation delay, which affects the speed and efficiency of arithmetic operations, particularly in low voltage conditions and area usage.
Innovation Solution
A novel full adder circuit design incorporating a mirror type structure with reduced stacked transistors in pull-up and pull-down networks, optimizing logic operations to minimize delay and enhance performance under varying voltage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional full adder circuit structures are used, then the circuit can perform full addition operations, but the calculation delay is large and the operation speed is slow
Solution Approach 1:
The full adder circuit is divided into two independent modules: a carry-out generating circuit that computes Co based on inputs A, B, and Ci, and a sum bit generating circuit that computes Sum based on the same inputs and the carry-out signal. This segmentation allows parallel computation of carry and sum, reducing overall calculation delay and improving operational speed.
2Reliability
If more stacked transistors are used in pull-up and pull-down networks, then the logic operation capability is enhanced, but the circuit delay increases and low voltage robustness deteriorates
Solution Approach 1:
The circuit employs parameter optimization by limiting the number of stacked transistors in the pull-up and pull-down networks to at most two. This parameter change reduces the voltage division effect and signal degradation that occur with more stacked transistors, thereby improving low-voltage robustness while simultaneously reducing logic gate delay and enhancing overall circuit performance.
3Speed
If the full adder circuit is designed for high speed operation, then the calculation delay is reduced, but the circuit area increases
Solution Approach 1:
The sum bit generating circuit is designed to perform multiple functions: it generates the sum bit output and simultaneously drives the carry-out signal distribution. This multi-functionality reduces the need for separate dedicated circuits, thereby achieving high-speed operation with minimized circuit area occupancy.
4Loss of time
If conventional non-mirror type full adder structures are used, then the circuit design is simpler, but the delay reduction effectiveness is limited
Solution Approach 1:
The patent employs an asymmetric mirror-type circuit structure where the pull-up and pull-down networks are designed with complementary but not identical configurations. This asymmetric design optimizes the balance between rising and falling edge delays, achieving superior delay reduction effectiveness compared to symmetric conventional designs, while the mirroring principle maintains structural regularity to limit complexity increase.
Data Source
AI summary
A full adder circuit includes a carry out generating circuit and a sum bit generating circuit. The carry out generating circuit is configured to generate a first output signal based on a first input signal, a second input signal and a third input signal. The sum bit generating circuit is configured to receive the first output signal and generate a second output signal based on the first input signal, the second input signal, the third input signal and the first output signal. The first output signal and the second output signal provide results of an arithmetic operation on the first input signal, the second input signal and the third input signal. The sum bit generating circuit includes a first pull-up network and a first pull-down network. There are at most two stacked transistors in at one or both of the first pull-up network and the first pull-down network.