Reflective Display Mirror Hinge Memory Reduction via Duty Cycle Balancing
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Solution Overview
Problem
Reflective technology displays experience image artifacts due to hinge memory in mirrors, which is exacerbated by asymmetric landed duty cycles, leading to reduced lifespan and mura artifacts.
Innovation Solution
Implementing a duty cycle balancing method during off periods by setting mirrors to both on and off positions to achieve a 50/50 balance, reducing the likelihood of hinge memory without requiring complex counter-bitplanes, thus saving power and extending the display's useful lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mirrors are directed to on or off position multiple times over the display lifetime, then the display can function normally, but asymmetric landed duty cycles accumulate causing hinge memory and image artifacts
Solution Approach 1:
The patent implements periodic duty cycle balancing during off periods by alternating mirror positions between on and off states. This periodic action counteracts asymmetric landed duty cycles that would otherwise accumulate over time, preventing hinge memory effects while maintaining normal display functionality throughout the device lifetime.
2Reliability
If counter-bitplanes are used to balance landed duty cycles, then hinge memory is reduced, but power consumption and processing bandwidth increase
Solution Approach 1:
Instead of continuously balancing duty cycles through complex counter-bitplanes during active periods, the patent applies partial balancing action during off periods only. This approach achieves sufficient hinge memory reduction while avoiding the excessive power consumption and processing bandwidth requirements of continuous balancing methods.
Solution Approach 2:
The patent extracts the duty cycle balancing function from the main active display operation and relocates it to off periods. This separation allows the display to function normally during active periods while performing balancing operations during idle off periods, reducing overall power consumption and processing demands.
3Reliability
If complex counter-bitplanes are implemented to balance duty cycles, then hinge memory is reduced, but device complexity increases
Solution Approach 1:
The patent implements simplified duty cycle balancing during off periods rather than complex continuous balancing. This partial action approach achieves adequate hinge memory reduction without requiring complex counter-bitplane circuits, processing bandwidth, or sophisticated control logic that would increase device complexity.
Data Source
AI summary
A device may include an electronic display to display image frames. The display may include illuminators that generate light and mirrors that selectively direct the light to pixel locations based bitplanes that set the arrangement of the mirrors. Additionally, the device may include duty cycle balancing circuitry that generates and provides duty cycle balancing signals to the electronic display. In response to the duty cycle balancing signals, the electronic display is implements balancing on bitplanes during at least a first portion of off periods during the image frames and implements balancing off bitplanes during at least a second portion of the off periods such that, in the aggregate, a ratio of respective on times of the mirrors to respective off times of the mirrors is balanced across the image frames during the off periods.