Mirror Image Landing Regions for 3D IC Interlayer Conductors

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Solution Overview

Problem

In 3-D integrated circuits, as the number of active layers increases, the formation of interlayer conductors becomes more difficult due to their tapering length, which reduces the landing window between the interlayer conductor and the landing region on the active layer, making reliable electrical contact challenging.

Innovation Solution

The implementation of a 3-D structure with alternating levels of insulating and active layers, where interlayer conductors pass through an insulating layer to contact mirror image stairstep arrangements of landing regions, maintaining a stable landing window by eliminating the need for openings adjacent to tall, tapered etch stop sidewalls, and using insulating sleeves to separate conductors from the insulating layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of active layers is increased to enhance 3-D integrated circuit functionality, then the circuit capability is improved, but the interlayer conductor tapers to a smaller diameter making reliable contact difficult

Engineering Contradiction:

Improvecircuit capabilityVSAvoidcontact reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent inverts the conventional approach by making the landing region smaller than the interlayer conductor opening. This reversal allows the interlayer conductor to maintain a larger diameter throughout its length while still achieving reliable contact, solving the tapering problem that occurs when the opening is smaller than the conductor.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces asymmetry in the contact structure by using different dimensions for the interlayer conductor opening and the landing region. The opening is made larger than the landing region, creating an asymmetric relationship that enables the conductor to maintain its diameter while making contact.

Inventive Principle:

Principle #4Asymmetry

2Adaptability or versatility

If the interlayer conductor length is increased to reach more active layers, then the connectivity is improved, but the conductor diameter decreases due to tapering

Engineering Contradiction:

ImproveconnectivityVSAvoidconductor diameter

Core Design Contradiction:

Adaptability or versatilityVSArea of moving object

Solution Approach 1:

The patent reverses the conventional dimensioning relationship by making the opening larger than the conductor rather than smaller. This inversion allows the conductor to maintain its diameter over increased lengths while still making reliable contact through the larger opening to the appropriately sized landing region.

Inventive Principle:

Principle #13The other way round (Inversion)

3Manufacturing precision

If the opening size is reduced to match the landing region, then the precision is improved, but the processing window is reduced making reliable contact difficult

Engineering Contradiction:

Improvelanding precisionVSAvoidprocessing window

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent inverts the conventional approach by making the opening larger than the landing region. This reversal provides a larger processing window for forming the opening while still achieving precise contact, as the larger opening is more tolerant to manufacturing variations.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the dimensional parameters of the opening and landing region to create an asymmetric relationship. By making the opening larger than the landing region, the processing window is enlarged while maintaining the precision needed for reliable contact.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9425209B1Multilayer 3-D structure with mirror image landing regions

Publication Date: 2016.08.23 MACRONIX INTERNATIONAL CO LTD

AI summary

An integrated circuit includes blocks and global lines overlying the blocks. The blocks include a plurality of levels including two dimensional arrays of memory cells having horizontal lines and being intersected by vertical lines coupled to corresponding memory cells. Levels include contact pads communicating with horizontal lines for a given block. The global lines include connectors. Connectors coupled to given global lines are coupled to landing areas on corresponding contact pads of the blocks. The blocks include first and second blocks disposed so that a first set of the contact pads associated with the first block are next to a second set of contact pads associated with the second block. The landing areas of the contact pads of the first and second blocks are mirror image surfaces of one another. The horizontal lines can be bit lines and the vertical lines can be word lines.