Semiconductor Memory Device Mirror Package DQ Pin Routing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Double-side mounted semiconductor memory devices face challenges in data transfer speed due to longer interconnecting wires between common DQ pins on opposite surfaces of a substrate, leading to data discrepancies between normal and mirror packages when connected perpendicular to the substrate surface.

Innovation Solution

Incorporating a connection change circuit within the mirror package that alters the connection path between input and output lines based on a specific connection rule, ensuring data consistency by exchanging DQ pins internally to match the connection pattern of the normal package or controller, thus maintaining data integrity and reducing wire length.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If packages are mounted on both surfaces of substrate with common DQ pins connected perpendicular to substrate surface, then data transfer can be achieved between normal and mirror packages, but wire length becomes longer causing data transfer speed degradation

Engineering Contradiction:
Improvedata transfer speedVSAvoidinterconnecting wire length
Core Design Contradiction:
SpeedVSLength of stationary object

Solution Approach 1:

The patent transitions from perpendicular connection (through substrate thickness) to planar connection (along substrate surface). By routing DQ pins parallel to the substrate surface rather than perpendicular, the connection path changes from a short but long-distance trace through the substrate to a longer but shorter-distance trace on the surface, effectively reducing signal propagation delay and improving data transfer speed.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Instead of connecting DQ pins in the conventional perpendicular direction through the substrate, the patent inverts the connection approach by using planar routing on the substrate surface. This inversion of the connection dimension transforms the problem from long wire length to optimized signal path, resolving the speed-wire length contradiction.

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If DQ pins are connected perpendicular to substrate surface in double-side mounted configuration, then connection between normal and mirror packages is established, but data discrepancies occur between packages

Engineering Contradiction:
Improvedata consistencyVSAvoidconnection configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by configuring DQ pin connections differently for normal and mirror packages. Specifically, odd-numbered DQ pins of the mirror package are connected to even-numbered DQ pins of the normal package, and vice versa. This asymmetric cross-connection pattern ensures that data transferred between packages maintains consistency and avoids discrepancies, while the systematic nature of the asymmetry keeps the configuration manageable.

Inventive Principle:
Principle #4Asymmetry

3Productivity

If common DQ pins are used for both normal and mirror packages, then data transfer is enabled, but wire length increases leading to signal integrity issues

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidinterconnecting wire length
Core Design Contradiction:
ProductivityVSLength of stationary object

Solution Approach 1:

The patent resolves the productivity-wire length contradiction by changing the connection dimension from perpendicular to planar. This allows common DQ pins to be shared between normal and mirror packages while reducing the effective wire length through optimized routing on the substrate surface, thereby maintaining data transfer capability with improved signal integrity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11322480B2Semiconductor memory device
Publication Date: 2022.05.03 KIOXIA CORP
  • US11322480B2 patent drawing
  • US11322480B2 patent drawing
  • US11322480B2 patent drawing

AI summary

A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.