Mirror Register Buffer Bypasses Internal Bus for Data Transfer
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Solution Overview
Problem
Current semiconductor devices face inefficiencies in data transfer and data organization due to the need for CPU involvement in specifying transfer addresses and the subsequent longer processing times, especially when using DMA/DTC controllers require CPU intervention for data reduction.
Innovation Solution
A semiconductor device configuration that includes a processor, memory, external interface, register, mirror register buffer, and internal buses, where the mirror register buffer assigns consecutive addresses to data from the register, allowing direct transfer to memory without using the internal bus, thereby reducing data transfer and organization time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CPU is used for data transfer, then data transfer can be performed with flexible address specification, but data transfer time becomes longer and CPU cannot perform other processing
Solution Approach 1:
The system segments the data transfer function by separating address specification (performed by CPU) from actual data transfer (performed by dedicated transfer circuit). This allows the CPU to specify addresses flexibly while the transfer circuit handles the actual data movement independently, resolving the contradiction between flexible address specification and fast data transfer.
2Speed
If DMA/DTC controller is used for data transfer, then data transfer speed is improved, but CPU involvement is still required for data reduction increasing total processing time
Solution Approach 1:
The transfer circuit performs data transfer in advance and independently of CPU intervention. By pre-configuring transfer parameters and executing transfers autonomously, the system eliminates the need for CPU involvement in data reduction operations, thereby reducing total processing time while maintaining high transfer speeds.
3Device complexity
If data transfer goes through internal bus, then system architecture is simple, but data transfer time increases
Solution Approach 1:
A dedicated transfer circuit is introduced as an intermediary component between the data source and destination. This specialized mediator handles data transfer operations independently of the internal bus, providing a faster transfer path while maintaining overall system architectural simplicity through modular design.
Data Source
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AI summary
A semiconductor device capable of shortening a time required for data transfer and data organizing is provided. The solid state device includes a processor (10), a memory (30), an external interface (40), registers (51, 52, 53) for storing data received by the external interface (40), a mirror register buffer (60), a processor (10), a memory (30), an external interface (40), registers (51, 52, 53), and an internal bus (80) connected to the mirror register buffer (60). Registers (51, 52, 53) output data to the mirror register buffer (60) without going through the internal bus (80). Mirror register buffer (60) gives the data input from the registers (51, 52, 53) an address in a mirror register buffer (60) different from the address allocated to the register (51, 52, 53), and transfers the data to the memory (30) without passing through the internal bus (80).