Mirror-Symmetric Stacked Transistors Without MOL Interconnects
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Solution Overview
Problem
Conventional stacked semiconductor devices face challenges in miniaturization due to middle-of-the-line (MOL) structures that limit area reduction and cause misalignment issues, as they require direct or indirect connections between upper and lower stack transistors, hindering efficient use of space and causing misalignment problems.
Innovation Solution
A mirror-symmetric stacked semiconductor device structure is developed, where the first and second transistors are formed with vertically mirror-symmetric gate structures, eliminating the need for MOL structures between them, allowing for a more compact design and easier formation of lateral contacts and backside interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If simple stacking or layering of two semiconductor devices is used, then area reduction is achieved, but middle-of-the-line (MOL) structures are required to connect lower-stack and upper-stack transistors, preventing 50% area reduction
Solution Approach 1:
The patent extracts and eliminates the MOL structures (top epi contact structure CA, bottom epi contact structure CR, gate contact structure CB, and gate pattern contact structure CS) from the stacked device configuration. By removing these intermediate connection structures, the invention achieves direct vertical stacking of transistors without requiring complex middle-of-the-line interconnects, thereby enabling 50% or greater area reduction while simplifying device complexity
Solution Approach 2:
The patent transitions from a two-dimensional planar connection approach to a three-dimensional vertical stacking approach. By arranging transistors in vertical stacks with direct upper-lower positioning and eliminating the need for lateral MOL connections, the invention utilizes the vertical dimension to achieve compact integration and 50% area reduction
2Reliability
If MOL structures are used to connect upper and lower stack transistors, then electrical connection is achieved, but misalignment issues occur and area reduction is limited
Solution Approach 1:
The patent removes the MOL structures that cause misalignment issues. By eliminating the top epi contact structure CA, bottom epi contact structure CR, gate contact structure CB, and gate pattern contact structure CS, the invention avoids the alignment problems inherent in lateral connections while maintaining reliable vertical electrical connections through direct transistor stacking
Solution Approach 2:
Instead of making lateral connections between stacked transistors (the conventional approach), the patent inverts the connection strategy by using direct vertical connections. This inversion eliminates misalignment issues because vertical stacking naturally aligns connection points without requiring precise lateral positioning of MOL structures
3Productivity
If conventional stacked device structure is used, then three-dimensional integration is achieved, but area reduction by 50% or more cannot be realized due to MOL structures
Solution Approach 1:
The patent extracts and removes the MOL structures (epi contact structures CA and CR, gate contact structure CB, and gate pattern contact structure CS) that prevent maximum area reduction. By eliminating these intermediate connection layers, the invention achieves direct vertical stacking that enables 50% or greater area reduction while maintaining high integration efficiency
Solution Approach 2:
The patent merges the upper and lower stack transistors into a more compact configuration by eliminating MOL structures. This merging combines the transistor stacks directly vertically, reducing the overall device area by 50% or more while maintaining functional integration through direct vertical connections
Data Source
AI summary
A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.