Mirror-Transistor Overcurrent Circuit for Peak Current Suppression

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Solution Overview

Problem

Conventional overcurrent protection circuits in power supply devices face challenges in suppressing peak current while improving load variation characteristics, as their operation timing is uniquely determined, making it difficult to regulate peak current effectively.

Innovation Solution

The power supply device incorporates multiple output transistors and mirror transistors with shifted operation timings, controlled by separate gate drive signals, and a resistor to regulate phase characteristics, allowing for suppression of peak current and improved load response by adjusting the mirror current ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single overcurrent protection circuit with fixed operation timing is used, then the circuit structure is simple, but the peak current cannot be effectively suppressed and load response characteristics are poor

Engineering Contradiction:
Improvepeak current suppressionVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The single overcurrent protection circuit is divided into multiple independent protection circuits (first overcurrent protection circuit and second overcurrent protection circuit), each with separate operation timing. This segmentation allows different circuits to operate at different stages, effectively suppressing peak current while maintaining manageable circuit complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces dynamic control by making the operation timing of each protection circuit adjustable and independent. The first and second protection circuits can be activated at different times based on operational conditions, enabling adaptive peak current suppression rather than fixed timing operation, thus improving reliability without excessive complexity.

Inventive Principle:
Principle #15Dynamics

2Reliability

If multiple protection circuits with different operation timings are implemented, then peak current suppression is improved, but the control complexity increases

Engineering Contradiction:
Improveload response characteristicsVSAvoidcontrol complexity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The protection circuits are designed to operate at predetermined timing sequences - the first protection circuit operates during initial startup, and the second protection circuit operates subsequently. This preliminary arrangement of operation timing simplifies control by eliminating the need for complex real-time decision-making, while still achieving improved load response characteristics through the staged protection approach.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If the operation timing is fixed, then the control is simple, but it is difficult to regulate peak current effectively during startup and load variations

Engineering Contradiction:
Improvecontrol simplicityVSAvoidpeak current regulation
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The invention implements periodic or staged action by activating different protection circuits at different time periods - the first overcurrent protection circuit operates during the initial startup period, and the second circuit operates during subsequent periods. This periodic approach maintains control simplicity through clear timing separation while effectively regulating peak current at each operational stage.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20240275160A1Overcurrent protection circuit and power supply device
Publication Date: 2024.08.15 ROHM CO LTD
  • US20240275160A1 patent drawing
  • US20240275160A1 patent drawing
  • US20240275160A1 patent drawing

AI summary

An overcurrent protection circuit includes a first mirror transistor configured to be driven by a first drive signal, common to a first output transistor, so as to pass a first mirror current, a second mirror transistor configured to be driven by a second drive signal so as to pass a second mirror current, a resistor configured to be connected between a control terminal of each of the first output transistor and the first mirror transistor and a control terminal of the second mirror transistor, and a current restriction unit configured to control the first drive signal such that a sense current, which is a total of the first mirror current and the second mirror current, is restricted to values equal to or less than a predetermined upper limit value.