Mirrored Chiplet Layout for Precise 3D Stack Alignment
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling to three-dimensional (3D) integration due to limitations in transistor density, alignment errors, and high thermal budgets, which hinder the development of efficient and reliable vertical stacking of chiplets for multi-chip integrated circuits.
Innovation Solution
A method involving the formation of chiplets on a substrate with mirrored alignment features and semiconductor structures across a shared reference line, allowing for precise alignment and bonding of chiplets in a vertical stack, reducing alignment errors and thermal budget constraints, and utilizing a 2D projection process adapted into design algorithms for minimal misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D semiconductor circuits are used with increased transistor density, then scaling efforts improve transistor capacity per unit area, but alignment errors and thermal budget constraints worsen as scaling enters single digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertical stacking by forming chiplets in a first plane and stacking them vertically with subsequent chiplets in second and third planes. This dimensional transition allows continued scaling and increased transistor density while avoiding the alignment errors that plague single-digit nanometer 2D fabrication nodes.
Solution Approach 2:
The patent divides the semiconductor device into multiple discrete chiplets (first chiplet, second chiplet, third chiplet) that can be fabricated separately on the same substrate and then stacked vertically. This segmentation allows each chiplet to be optimized independently and reduces the cumulative alignment errors that would occur in monolithic 3D integration.
2Productivity
If vertical stacking of chiplets is implemented to achieve 3D integration, then transistor density and performance improve, but alignment precision between stacked chiplets becomes more difficult to maintain
Solution Approach 1:
The patent forms all chiplets (first, second, and third chiplets) simultaneously on the same substrate in predetermined locations before separation and stacking. This preliminary co-fabrication ensures that alignment features and semiconductor structures are pre-aligned according to the mirrored layout, eliminating the need for post-fabrication alignment adjustments and reducing cumulative alignment errors.
Solution Approach 2:
The patent employs a mirrored layout where the second chiplet has alignment features and semiconductor structures that are mirror images of the first chiplet across a reference line, and the third chiplet mirrors the second chiplet. This asymmetric mirrored design enables precise alignment during vertical stacking by providing complementary alignment features that naturally guide the stacking process.
3Device complexity
If multiple fabrication processes are used for 3D stacking, then vertical integration is achieved, but thermal budget constraints and process complexity increase
Solution Approach 1:
The patent combines multiple chiplet fabrication processes into a single unified fabrication sequence where first, second, and third chiplets are formed simultaneously on the same substrate using the same fabrication processes. This merging eliminates the need for separate high-temperature processing steps for each chiplet, thereby reducing the overall thermal budget while achieving complex vertical integration.
Data Source
AI summary
In certain embodiments, a method for designing a semiconductor device includes generating a 2D design for fabricating chiplets on a substrate. The chiplets are component levels for a multi-chip integrated circuit. The 2D design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The first and second chiplets are adjacent on the substrate. The second layout is a mirror image of the first layout across a reference line shared by the first and second chiplets. The first surfaces of the first and second chiplets are both either top or bottom surfaces. The method further includes generating one or more photomasks according to the design.