Mirrored GPU Domain for 3D FDTD Simulation Bottlenecks
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Solution Overview
Problem
Existing methods for 3D finite-difference time-domain (FDTD) electromagnetic simulations face significant bottlenecks due to the large size of the arrays used, which limits the acceleration benefits of GPU parallelization.
Innovation Solution
The method involves creating a mirror set of 3D arrays on a GPU, allowing the CPU to send instructions for updating specific arrays during the simulation, and then copying the updated arrays back to the CPU upon completion, thereby reducing data transfer bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GPU parallelization is used for 3D FDTD simulation update operations, then processing speed is improved, but data transfer bottlenecks between CPU and GPU worsen
Solution Approach 1:
The patent segments the large 3D arrays into multiple smaller sub-arrays or blocks that can be processed independently. By dividing the computational domain into manageable segments, the data transfer volume between CPU and GPU is reduced while maintaining parallel processing benefits. Each segment can be updated independently on the GPU with minimal coordination overhead.
Solution Approach 2:
The patent performs preliminary actions by pre-allocating and pre-configuring the array structures on the GPU before the main simulation begins. Memory is pre-allocated, boundary conditions are pre-set, and the computational grid is pre-established on the GPU, eliminating the need for repeated data transfers during the simulation runtime.
Solution Approach 3:
The patent introduces a new dimensional aspect by implementing a hybrid memory architecture that combines CPU memory and GPU memory with a sophisticated management layer. This additional dimension of memory management allows intelligent data placement and transfer optimization, reducing bottlenecks by selecting the most efficient data path for each operation.
2Measurement precision
If large 3D arrays are used for FDTD simulation, then simulation accuracy is improved, but memory bandwidth requirements worsen
Solution Approach 1:
The patent divides the large 3D arrays representing electromagnetic fields into smaller spatial segments or frequency bands that can be processed independently. This segmentation reduces the memory bandwidth required for each processing operation while maintaining the overall simulation accuracy through coordinated processing of all segments.
Solution Approach 2:
The patent applies local quality by using different data representations or precision levels for different regions of the simulation domain. Areas requiring high accuracy use full-precision arrays, while other regions use reduced precision or compressed representations, optimizing the balance between overall simulation accuracy and memory bandwidth consumption.
3Ease of manufacture
If CPU sequential processing is used for FDTD simulation, then implementation simplicity is improved, but processing speed worsens
Solution Approach 1:
The patent introduces an intermediary layer or abstraction interface between the CPU and GPU that simplifies the complexity of GPU programming. This intermediary handles memory management, data transfer coordination, and parallel operation scheduling, allowing developers to write relatively simple code that automatically leverages GPU parallel processing capabilities without directly managing complex GPU kernels.
Data Source
AI summary
Methods, systems, and non-transitory computer-readable media circumvent bottlenecking of graphics processing unit (GPU) parallelization during three-dimensional (3D) finite-difference time-domain (FDTD) simulation. Before running the 3D FDTD simulation, a central processing unit (CPU) creates 3D arrays and a mirror set of the 3D arrays, and stores the mirror set on a GPU. During runtime of the 3D FDTD simulation, the CPU sends, to the GPU, instructions to update arrays of interest of the mirror set on the GPU, which simultaneously updates array elements of 3D electromagnetic field components of each array in the arrays of interest. Upon completion of the 3D FDTD simulation, the CPU copies the updated arrays of interest from the GPU to the CPU by instructing the GPU to copy the updated arrays of interest from the GPU to corresponding mirror arrays pointed to on RAM, and writes the updated arrays of interest to an output file.