Mirrored Memory Error Detection Using CRC
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Solution Overview
Problem
Current memory systems, including mirrored memory systems, are ineffective in detecting multi-bit errors using Hamming error correction codes, leading to flawed error correction routines and undetected incorrect data, especially when address line failures occur.
Innovation Solution
A system and method utilizing a memory subsystem with parallel memory channels that employs a cyclic redundancy code (CRC) generated from both data bits and address bits, stored using horizontal or vertical mirroring schemes, allowing for improved error detection and correction by mirroring the CRC between channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Hamming error correction codes are used in mirrored memory systems, then single bit errors can be identified, but multi-bit errors cannot be detected and may produce flawed error correction routines that are recognized as correct
Solution Approach 1:
The patent combines Hamming error correction codes with cyclic redundancy check (CRC) codes to create a hybrid error detection and correction system. The Hamming code handles single-bit error correction while the CRC component detects multi-bit errors that Hamming codes cannot identify, thereby resolving the limitation of using Hamming codes alone in mirrored memory systems.
Solution Approach 2:
The error detection system uses a composite approach by integrating two different error detection mechanisms (Hamming codes and CRC codes) into a unified system. This composite error detection scheme leverages the strengths of both methods: Hamming codes for single-bit correction and CRC for multi-bit error detection, preventing flawed correction routines from being executed.
2Measurement precision
If data comparison is performed during each read cycle to detect errors, then error detection accuracy improves, but memory bandwidth and operation speed decrease
Solution Approach 1:
The patent generates cyclic redundancy check (CRC) codes during the data writing process rather than during reading. This preliminary error detection preparation allows the system to quickly verify data integrity during read operations by simply comparing the stored CRC with a newly calculated CRC, eliminating the need for time-consuming data bit comparisons and preserving memory bandwidth.
Solution Approach 2:
The patent extracts the error detection function into a separate CRC code that is independently calculated and stored alongside the data. During read operations, only the CRC codes need to be compared rather than the entire data set, significantly reducing the computational overhead and maintaining high memory bandwidth while ensuring accurate error detection.
3Reliability
If address line failures occur causing can address failure, then Hamming error correction codes cannot detect the error, but cyclic redundancy code generated from both data bits and address bits can detect the error
Solution Approach 1:
The cyclic redundancy check (CRC) code serves multiple functions: it detects multi-bit errors in data, detects address line failures, and works in conjunction with Hamming codes for comprehensive error handling. This multi-functional approach enhances reliability without requiring separate detection mechanisms for different error types, thereby managing device complexity effectively.
4Adaptability or versatility
If mirrored memory is used to store duplicate copies of data, then data availability improves, but memory space requirements increase
Solution Approach 1:
The patent implements mirrored memory by creating duplicate copies of data and storing them in separate memory modules. Each memory module contains identical data copies, allowing the system to access data from either module. This copying approach ensures high data availability and fault tolerance, as data can be retrieved from the non-failed module if one module experiences errors.
Data Source
AI summary
A system and method is disclosed for detecting errors in memory. A memory subsystem that includes a set of parallel memory channels is disclosed. Data is saved such that a duplicate copy of data is saved to the opposite memory channel according to a horizontal mirroring scheme or a vertical mirroring scheme. A cyclic redundancy code is generated on the basis of the data bits and address bits. The generated cyclic redundancy code and a copy of the cyclic redundancy code are saved to the memory channels according to a horizontal mirroring scheme or a vertical mirroring scheme.